OUT_CS_REG(0x4F34, 0x00000000);
OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
-OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000);
R300_PACIFY;
-OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x21030003);
OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
-OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000);
R300_PACIFY;
-OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
/* XXX translate these back into normal instructions */
OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-OUT_CS_REG(R300_RB3D_COLORPITCH0, (w >> 1) | R300_COLOR_TILE_ENABLE |
+/* XXX this should not be so rigid */
+OUT_CS_REG(R300_RB3D_COLORPITCH0, (w / 4) | R300_COLOR_TILE_ENABLE |
R300_COLOR_FORMAT_ARGB8888);
OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
/* XXX Packet3 */
OUT_CS_32F(1.0);
/* XXX figure out why this is 0xA and not 0x2 */
-/* XXX OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
-OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
+OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+/* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
R300_PACIFY;