top: connect UART IRQ

diff --git a/top.py b/top.py
index 3a28d54bc254ff507a7ef7b8406c5734d22430b3..7014158efc82222adc67654eb6de530ed6e88fd6 100644 (file)
--- a/top.py
+++ b/top.py
@@ -39,7 +39,11 @@ def get():
        uart0 = uart.UART(0, clk_freq, baud=115200)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
        
-       frag = autofragment.from_local()
+       interrupts = Fragment([
+               cpu0.interrupt[0].eq(uart0.events.irq)
+       ])
+       
+       frag = autofragment.from_local() + interrupts
        src_verilog, vns = verilog.convert(frag,
                {clkfx_sys.clkin, reset0.trigger_reset},
                name="soc",