info->min_vgpr_alloc = 4;
info->max_vgpr_alloc = 256;
- info->vgpr_alloc_granularity = info->chip_class >= GFX10 ? 8 : 4;
+ info->wave64_vgpr_alloc_granularity = 4;
info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
printf(" sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
printf(" min_vgpr_alloc = %i\n", info->min_vgpr_alloc);
printf(" max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
- printf(" vgpr_alloc_granularity = %i\n", info->vgpr_alloc_granularity);
+ printf(" wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
printf("Render backend info:\n");
printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
uint32_t sgpr_alloc_granularity;
uint32_t min_vgpr_alloc;
uint32_t max_vgpr_alloc;
- uint32_t vgpr_alloc_granularity;
+ uint32_t wave64_vgpr_alloc_granularity;
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
properties->maxVgprAllocation =
pdevice->rad_info.max_vgpr_alloc;
properties->vgprAllocationGranularity =
- pdevice->rad_info.vgpr_alloc_granularity;
+ pdevice->rad_info.wave64_vgpr_alloc_granularity;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
chunk->wavefronts_per_simd = rad_info->max_wave64_per_simd;
chunk->minimum_vgpr_alloc = rad_info->min_vgpr_alloc;
- chunk->vgpr_alloc_granularity = rad_info->vgpr_alloc_granularity;
+ chunk->vgpr_alloc_granularity = rad_info->wave64_vgpr_alloc_granularity;
chunk->minimum_sgpr_alloc = rad_info->min_sgpr_alloc;
chunk->sgpr_alloc_granularity = rad_info->sgpr_alloc_granularity;