back.rtlil: fix swapped operands in sync assign.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 490e3e7fcde97c953243cb49a3741f7e3b66a21a..0e06d2065c5ab37b0e141d2020aefc5b35f29ab0 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -495,9 +495,9 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
                 for trigger in triggers:
                     with process.sync(*trigger) as sync:
                         for signal in signals:
-                            rhs_sigspec = xformer(signal)
+                            lhs_sigspec = xformer(signal)
                             with xformer.lhs():
-                                sync.update(xformer(signal), rhs_sigspec)
+                                sync.update(lhs_sigspec, xformer(signal))
 
     # Finally, collect the names we've given to our ports in RTLIL, and correlate these with
     # the signals represented by these ports. If we are a submodule, this will be necessary