Added english language description, spaces and brackets for lwzu instruction

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index f2339b89d66dbb917b4a45384d10e2ef4ba0352b..502e29c204b2cedbac2c3b88de2ac44e8c21c1b0 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -373,6 +373,16 @@ Pseudo-code:
     RT <- [0]*32 || MEM(EA, 4)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D. The
+    word in storage addressed by EA is loaded into
+    RT[32:63]. RT[0:31] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None