targets: revert use of integers in clocks/timings

diff --git a/targets/minispartan6.py b/targets/minispartan6.py
index 82e9fb783010699be7b64452ebbca9071867e520..876b77d1f1d27e7241356b33ee0ff3b3ffad2322 100644 (file)
--- a/targets/minispartan6.py
+++ b/targets/minispartan6.py
@@ -15,7 +15,7 @@ class _CRG(Module):
                self.clock_domains.cd_sys = ClockDomain()
                self.clock_domains.cd_sys_ps = ClockDomain()
 
-               f0 = 32*1e6
+               f0 = 32*1000000
                clk32 = platform.request("clk32")
                clk32a = Signal()
                self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
@@ -35,7 +35,7 @@ class _CRG(Module):
                        i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
                        p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
                        i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
-                       p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
+                       p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
                        i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
                        o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
                        o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
@@ -64,7 +64,7 @@ class BaseSoC(SDRAMSoC):
        default_platform = "minispartan6"
 
        def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
-               clk_freq = 80*1e6
+               clk_freq = 80*1000000
                SDRAMSoC.__init__(self, platform, clk_freq,
                        with_integrated_rom=True,
                        sdram_controller_settings=sdram_controller_settings,

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index d12a1a2b81b8f2f2af135f4e13bf2eb62d3cf5aa..ccdd499937eae91c85be28803c0d6c1cf9ef19b2 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -20,7 +20,7 @@ class _CRG(Module):
                self.clk4x_wr_strb = Signal()
                self.clk4x_rd_strb = Signal()
 
-               f0 = 50*1e6
+               f0 = 50*1000000
                clk50 = platform.request("clk50")
                clk50a = Signal()
                self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
@@ -41,7 +41,7 @@ class _CRG(Module):
                        i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
                        p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
                        i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
-                       p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
+                       p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
                        i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
                        o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
                        o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
@@ -91,7 +91,7 @@ class BaseSoC(SDRAMSoC):
        csr_map.update(SDRAMSoC.csr_map)
 
        def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
-               clk_freq = 75*1e6
+               clk_freq = 75*1000000
                if not kwargs.get("with_integrated_rom"):
                        kwargs["rom_size"] = 0x1000000 # 128 Mb
                SDRAMSoC.__init__(self, platform, clk_freq,

diff --git a/targets/ppro.py b/targets/ppro.py
index da27a6e2fa33b731dd4ab55f4a975bd346ba5c8e..556ddd02fc7917b890954fd91de7f05d8c482053 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -15,7 +15,7 @@ class _CRG(Module):
                self.clock_domains.cd_sys = ClockDomain()
                self.clock_domains.cd_sys_ps = ClockDomain()
 
-               f0 = 32*1e6
+               f0 = 32*1000000
                clk32 = platform.request("clk32")
                clk32a = Signal()
                self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
@@ -35,7 +35,7 @@ class _CRG(Module):
                        i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
                        p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
                        i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
-                       p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
+                       p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
                        i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
                        o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
                        o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
@@ -69,7 +69,7 @@ class BaseSoC(SDRAMSoC):
        csr_map.update(SDRAMSoC.csr_map)
 
        def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
-               clk_freq = 80*1e6
+               clk_freq = 80*1000000
                SDRAMSoC.__init__(self, platform, clk_freq,
                        cpu_reset_address=0x60000,
                        sdram_controller_settings=sdram_controller_settings,