Bugfix in verilog_defaults argument parser

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 19fc3c6afa6109b515f3db8cd533267fa1be59bd..e5917b97eb84bf09415d99035f40cab5c32fec39 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -407,7 +407,7 @@ struct VerilogDefaults : public Pass {
        }
        virtual void execute(std::vector<std::string> args, RTLIL::Design*)
        {
-               if (args.size() == 0)
+               if (args.size() < 2)
                        cmd_error(args, 1, "Missing argument.");
 
                if (args[1] == "-add") {