void
IdeController::intrPost()
{
- tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
}
void
IdeController::intrClear()
{
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
}
////
void
IdeDisk::intrPost()
{
+ DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n");
if (intrPending)
panic("Attempt to post an interrupt with one pending\n");
void
IdeDisk::intrClear()
{
+ DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n");
if (!intrPending)
panic("Attempt to clear a non-pending interrupt\n");
cpuPendingIntr = true;
DPRINTF(EthernetIntr, "posting cchip interrupt\n");
- tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
}
}
cpuPendingIntr = false;
DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
}
bool
virtual void postConsoleInt() = 0;
virtual void clearConsoleInt() = 0;
virtual Tick intrFrequency() = 0;
+ virtual void postPciInt(int line) = 0;
+ virtual void clearPciInt(int line) = 0;
};
#endif // __PLATFORM_HH_
io->clearPIC(0x10);
}
+void
+Tsunami::postPciInt(int line)
+{
+ this->cchip->postDRIR(line);
+}
+
+void
+Tsunami::clearPciInt(int line)
+{
+ this->cchip->clearDRIR(line);
+}
+
void
Tsunami::serialize(std::ostream &os)
{
virtual void clearConsoleInt();
/**
+ * Cause the chipset to post a cpi interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+ /**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/