done
fi
-h8s_files="archures.c coff-h8300.c coffcode.h cpu-h8300.c ChangeLog bfd-in2.h"
-if ( echo $* | grep keep\-h8s > /dev/null ) ; then
- for i in $h8s_files ; do
- if test ! -d $i && (grep sanitize-h8s $i > /dev/null) ; then
- if [ -n "${verbose}" ] ; then
- echo Keeping h8s stuff in $i
- fi
- fi
- done
-else
- for i in $h8s_files ; do
- if test ! -d $i && (grep sanitize-h8s $i > /dev/null) ; then
- if [ -n "${verbose}" ] ; then
- echo Removing traces of \"h8s\" from $i...
- fi
- cp $i new
- sed '/start\-sanitize\-h8s/,/end-\sanitize\-h8s/d' < $i > new
- if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
- if [ -n "${verbose}" ] ; then
- echo Caching $i in .Recover...
- fi
- mv $i .Recover
- fi
- mv new $i
- fi
- done
-fi
-
for i in * ; do
if test ! -d $i && (grep sanitize $i > /dev/null) ; then
echo '***' Some mentions of Sanitize are still left in $i! 1>&2
* coff-h8300.c: Remove #if 0 code.
(compatable): Don't allow mixing/matching of different architectures.
-start-sanitize-h8s
* archures.c (bfd_mach_h8300s): Add.
* bfd-in2.h: Rebuilt.
* coff-h8300.c (funcvec_hash_newfunc): Handle H8/S too.
* cpu-h8300.c (h8300_scan): Likewise.
Add H8/S to bfd_h8300_arch list.
-end-sanitize-h8s
Tue Jun 18 14:42:58 1996 Klaus Kaempf <kkaempf@progis.de>
Added support for Alpha OpenVMS:
/* BFD library support routines for architectures.
- Copyright (C) 1990, 91-95, 1996 Free Software Foundation, Inc.
+ Copyright (C) 1990, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
.#define bfd_mach_i960_mc 4
.#define bfd_mach_i960_xa 5
.#define bfd_mach_i960_ca 6
-. {* start-sanitize-i960xl *}
-.#define bfd_mach_i960_xl 7
-. {* end-sanitize-i960xl *}
+.#define bfd_mach_i960_jx 7
.#define bfd_mach_i960_hx 8
.
. bfd_arch_a29k, {* AMD 29000 *}
. bfd_arch_sparc, {* SPARC *}
.#define bfd_mach_sparc 1
.{* The difference between v8plus and v9 is that v9 is a true 64 bit env. *}
-.#define bfd_mach_sparc_v8plus 2
-.#define bfd_mach_sparc_v8plusa 3 {* with ultrasparc add'ns *}
-.#define bfd_mach_sparc_v9 4
-.#define bfd_mach_sparc_v9a 5 {* with ultrasparc add'ns *}
+.#define bfd_mach_sparc_sparclet 2
+.#define bfd_mach_sparc_sparclite 3
+.#define bfd_mach_sparc_v8plus 4
+.#define bfd_mach_sparc_v8plusa 5 {* with ultrasparc add'ns *}
+.#define bfd_mach_sparc_v9 6
+.#define bfd_mach_sparc_v9a 7 {* with ultrasparc add'ns *}
.{* Nonzero if MACH has the v9 instruction set. *}
-.#define bfd_mach_sparc_v9_p(mach) ((mach) != bfd_mach_sparc)
+.#define bfd_mach_sparc_v9_p(mach) \
+. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a)
. bfd_arch_mips, {* MIPS Rxxxx *}
. bfd_arch_i386, {* Intel 386 *}
. bfd_arch_we32k, {* AT&T WE32xxx *}
. bfd_arch_h8300, {* Hitachi H8/300 *}
.#define bfd_mach_h8300 1
.#define bfd_mach_h8300h 2
+.#define bfd_mach_h8300s 3
. bfd_arch_powerpc, {* PowerPC *}
. bfd_arch_rs6000, {* IBM RS/6000 *}
. bfd_arch_hppa, {* HP PA RISC *}
. bfd_arch_arm, {* Advanced Risc Machines ARM *}
. bfd_arch_ns32k, {* National Semiconductors ns32000 *}
. bfd_arch_w65, {* WDC 65816 *}
-. {* start-sanitize-rce *}
-. bfd_arch_rce, {* Motorola RCE *}
-. {* end-sanitize-rce *}
. {* start-sanitize-arc *}
. bfd_arch_arc, {* Argonaut RISC Core *}
.#define bfd_mach_arc_base 0
extern const bfd_arch_info_type bfd_powerpc_arch;
extern const bfd_arch_info_type bfd_rs6000_arch;
extern const bfd_arch_info_type bfd_sh_arch;
-/* start-sanitize-rce */
-extern const bfd_arch_info_type bfd_rce_arch;
-/* end-sanitize-rce */
extern const bfd_arch_info_type bfd_sparc_arch;
extern const bfd_arch_info_type bfd_vax_arch;
extern const bfd_arch_info_type bfd_we32k_arch;
&bfd_powerpc_arch,
&bfd_rs6000_arch,
&bfd_sh_arch,
-/* start-sanitize-rce */
- &bfd_rce_arch,
-/* end-sanitize-rce */
&bfd_sparc_arch,
&bfd_vax_arch,
&bfd_we32k_arch,
bfd_arch_h8300, /* Hitachi H8/300 */
#define bfd_mach_h8300 1
#define bfd_mach_h8300h 2
+#define bfd_mach_h8300s 3
bfd_arch_powerpc, /* PowerPC */
bfd_arch_rs6000, /* IBM RS/6000 */
bfd_arch_hppa, /* HP PA RISC */
BFD_RELOC_SPARC_6,
BFD_RELOC_SPARC_5,
-/* Alpha ECOFF relocations. Some of these treat the symbol or "addend"
-in some special way.
+/* Alpha ECOFF and ELF relocations. Some of these treat the symbol or
+"addend" in some special way.
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
writing; when reading, it will be the absolute section symbol. The
addend is the displacement in bytes of the "lda" instruction from
reading, for convenience. */
BFD_RELOC_ALPHA_GPDISP_LO16,
+/* The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
+relocation except that there is no accompanying GPDISP_LO16
+relocation. */
+ BFD_RELOC_ALPHA_GPDISP,
+
/* The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
the assembler turns it into a LDQ instruction to load the address of
the symbol, and then fills in a register in the real instruction.
but it's not easily available here. */
if (bfd_get_mach (table->abfd) == bfd_mach_h8300)
table->offset += 2;
- else if (bfd_get_mach (table->abfd) == bfd_mach_h8300h)
+ else if (bfd_get_mach (table->abfd) == bfd_mach_h8300h
+ || bfd_get_mach (table->abfd) == bfd_mach_h8300s)
table->offset += 4;
else
return NULL;
#define SELECT_RELOC(x,howto) \
{ x.r_type = select_reloc(howto); }
-#define BADMAG(x) (H8300BADMAG(x)&& H8300HBADMAG(x))
+#define BADMAG(x) (H8300BADMAG(x) && H8300HBADMAG(x) && H8300SBADMAG(x))
#define H8300 1 /* Customize coffcode.h */
#define __A_MAGIC_SET__
if ((bfd_get_mach (abfd) == bfd_mach_h8300
&& value >= 0xff00
&& value <= 0xffff)
- || (bfd_get_mach (abfd) == bfd_mach_h8300h
+ || ((bfd_get_mach (abfd) == bfd_mach_h8300h
+ || bfd_get_mach (abfd) == bfd_mach_h8300s)
&& value >= 0xffff00
&& value <= 0xffffff))
{
/* The address is in 0xffff00..0xffffff inclusive on the h8300h,
then we can relax this mov.b */
- if (bfd_get_mach (abfd) == bfd_mach_h8300h
+ if ((bfd_get_mach (abfd) == bfd_mach_h8300h
+ || bfd_get_mach (abfd) == bfd_mach_h8300s)
&& value >= 0xffff00
&& value <= 0xffffff)
{
link_info,
input_section),
vectors_sec->contents + h->offset);
- else if (bfd_get_mach (input_section->owner) == bfd_mach_h8300h)
+ else if (bfd_get_mach (input_section->owner) == bfd_mach_h8300h
+ || bfd_get_mach (input_section->owner) == bfd_mach_h8300s)
bfd_put_32 (abfd,
bfd_coff_reloc16_get_value (reloc,
link_info,
takes 2 bytes on the h8300 and 4 bytes on the h8300h. */
if (bfd_get_mach (abfd) == bfd_mach_h8300)
h8300_coff_hash_table (info)->vectors_sec->_raw_size += 2;
- else if (bfd_get_mach (abfd) == bfd_mach_h8300h)
+ else if (bfd_get_mach (abfd) == bfd_mach_h8300h
+ || bfd_get_mach (abfd) == bfd_mach_h8300s)
h8300_coff_hash_table (info)->vectors_sec->_raw_size += 4;
}
}
}
#endif
-#ifdef COFF_WITH_PE
+#ifdef COFF_IMAGE_WITH_PE
/* In a PE image file, the s_paddr field holds the virtual size of a
section, while the s_size field holds the raw size. */
if (hdr->s_paddr != 0)
break;
#endif
-/* start-sanitize-h8s */
#ifdef H8300SMAGIC
case H8300SMAGIC:
arch = bfd_arch_h8300;
break;
#endif
-/* end-sanitize-h8s */
#ifdef SH_ARCH_MAGIC_BIG
case SH_ARCH_MAGIC_BIG:
case SH_ARCH_MAGIC_LITTLE:
case bfd_mach_h8300h:
*magicp = H8300HMAGIC;
return true;
-/* start-sanitize-h8s */
case bfd_mach_h8300s:
*magicp = H8300SMAGIC;
return true;
-/* end-sanitize-h8s */
}
break;
#endif
#endif
current->filepos = sofar;
-#ifdef COFF_WITH_PE
+#ifdef COFF_IMAGE_WITH_PE
/* With PE we have to pad each section to be a multiple of its
page size too, and remember both sizes. */
section.s_size = current->_raw_size;
#ifdef COFF_WITH_PE
+ section.s_paddr = 0;
+#endif
+#ifdef COFF_IMAGE_WITH_PE
/* Reminder: s_paddr holds the virtual size of the section. */
if (coff_section_data (abfd, current) != NULL
&& pei_section_data (abfd, current) != NULL)