cpu: Add support for Memory+Barrier instruction types in O3 cpu.

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 8f0249ced787ad7ca0515470856edf4e69aec4c1..8eba028d6fca11e9161f143c038438b9d5e3d765 100644 (file)
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -1157,11 +1157,17 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
             DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
                     tid, squashed_inst->seqNum, squashed_inst->pcState());
 
+            bool is_acq_rel = squashed_inst->isMemBarrier() &&
+                         (squashed_inst->isLoad() ||
+                           (squashed_inst->isStore() &&
+                             !squashed_inst->isStoreConditional()));
+
             // Remove the instruction from the dependency list.
-            if (!squashed_inst->isNonSpeculative() &&
-                !squashed_inst->isStoreConditional() &&
-                !squashed_inst->isMemBarrier() &&
-                !squashed_inst->isWriteBarrier()) {
+            if (is_acq_rel ||
+                (!squashed_inst->isNonSpeculative() &&
+                 !squashed_inst->isStoreConditional() &&
+                 !squashed_inst->isMemBarrier() &&
+                 !squashed_inst->isWriteBarrier())) {
 
                 for (int src_reg_idx = 0;
                      src_reg_idx < squashed_inst->numSrcRegs();