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enable misaligned Mem in ISACaller by default
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 1 Jan 2023 15:09:21 +0000 (15:09 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:16 +0000 (19:51 +0100)
src/openpower/decoder/isa/caller.py patch | blob | history

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 0d93f05ec6a0138516442832e6be292b70556d07..accce0c2b2e5f664e20c1de01b28497b41284793 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1173,7 +1173,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         self.last_op_svshape = False
 
         # "raw" memory
-        self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
+        self.mem = Mem(row_bytes=8, initial_mem=initial_mem, misaligned_ok=True)
         self.mem.log_fancy(kind=LogKind.InstrInOuts)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         # MMU mode, redirect underlying Mem through RADIX