This patch introduces ETE (Embedded Trace Extension) system registers for the AArch64...

gas           * testsuite/gas/aarch64/ete.d: New test.
              * testsuite/gas/aarch64/ete.s: New test.

opcodes       * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 565c131965b34677a47912709854eb74180db7d4..18c19baf3a59f925f1af6e63147b60f36c5ffc17 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+        * testsuite/gas/aarch64/ete.d: New test.
+        * testsuite/gas/aarch64/ete.s: New test.
+
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
         * testsuite/gas/aarch64/trbe-invalid.d: New test.

diff --git a/gas/testsuite/gas/aarch64/ete.d b/gas/testsuite/gas/aarch64/ete.d
new file mode 100644 (file)
index 0000000..511b4fb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ete.d
@@ -0,0 +1,18 @@
+#name: ETE System registers
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+: d5310880        mrs     x0, trcextinselr0
+[^:]+: d5310980        mrs     x0, trcextinselr1
+[^:]+: d5310a80        mrs     x0, trcextinselr2
+[^:]+: d5310b80        mrs     x0, trcextinselr3
+[^:]+: d5310a00        mrs     x0, trcrsr
+[^:]+: d5110880        msr     trcextinselr0, x0
+[^:]+: d5110980        msr     trcextinselr1, x0
+[^:]+: d5110a80        msr     trcextinselr2, x0
+[^:]+: d5110b80        msr     trcextinselr3, x0
+[^:]+: d5110a00        msr     trcrsr, x0

diff --git a/gas/testsuite/gas/aarch64/ete.s b/gas/testsuite/gas/aarch64/ete.s
new file mode 100644 (file)
index 0000000..72720ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ete.s
@@ -0,0 +1,15 @@
+/* ETE System registers.  */
+
+/* Read from system register.  */
+mrs x0, trcextinselr0
+mrs x0, trcextinselr1
+mrs x0, trcextinselr2
+mrs x0, trcextinselr3
+mrs x0, trcrsr
+
+/* Write to system register.  */
+msr trcextinselr0, x0
+msr trcextinselr1, x0
+msr trcextinselr2, x0
+msr trcextinselr3, x0
+msr trcrsr, x0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 291c52e54b860bc0226a73248bae9da52ba80b31..e9dfb78faad4022721fec2e8522943e5a7ee05fb 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+        * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 1be8d21642be6cce1ecebb01e6147ea63fe209b8..83afb1f9778ab7cff8f2105c95999e83847f89d7 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4319,6 +4319,12 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE("trbsr_el1",         CPENC (3,0,C9,C11,3),   0),
   SR_CORE("trbtrg_el1",        CPENC (3,0,C9,C11,6),   0),
 
+  SR_CORE ("trcextinselr0",    CPENC (2,1,C0,C8,4),    0),
+  SR_CORE ("trcextinselr1",    CPENC (2,1,C0,C9,4),    0),
+  SR_CORE ("trcextinselr2",    CPENC (2,1,C0,C10,4),   0),
+  SR_CORE ("trcextinselr3",    CPENC (2,1,C0,C11,4),   0),
+  SR_CORE ("trcrsr",           CPENC (2,1,C0,C10,0),   0),
+
   { 0, CPENC (0,0,0,0,0), 0, 0 }
 };