rs6000: Remove spe_acc and spefscr

We can also remove the two other SPE registers.

	* config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and
	SPEFSCR registers.
	* config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
	(enum rs6000_reg_type): Delete SPE_ACC_TYPE and SPEFSCR_REG_TYPE.
	(rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	(rs6000_dbx_register_number): Adjust.
	* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change to 115.
	(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
	Remove SPE_ACC and SPEFSCR.
	(REG_ALLOC_ORDER): Ditto.
	(FRAME_POINTER_REGNUM): Change to 111.
	(enum reg_class): Remove the SPE_ACC and SPEFSCR registers.
	(REG_CLASS_NAMES): Ditto.
	(REG_CLASS_CONTENTS): Delete the SPE_ACC and SPEFSCR registers.
	(REGISTER_NAMES): Ditto.
	(ADDITIONAL_REG_NAMES): Ditto.
	(rs6000_reg_names): Ditto.
	* config/rs6000/rs6000.md: Renumber some register number
	define_constants.

From-SVN: r248986

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 098541d217c9c432054e4e7702dbba6b56f494f6..45fc0ddc9fa42d5f10e7b349ed4a96bf7d47c3d5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,26 @@
+2017-06-07  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and
+       SPEFSCR registers.
+       * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
+       (enum rs6000_reg_type): Delete SPE_ACC_TYPE and SPEFSCR_REG_TYPE.
+       (rs6000_debug_reg_global): Adjust.
+       (rs6000_init_hard_regno_mode_ok): Adjust.
+       (rs6000_dbx_register_number): Adjust.
+       * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change to 115.
+       (FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
+       Remove SPE_ACC and SPEFSCR.
+       (REG_ALLOC_ORDER): Ditto.
+       (FRAME_POINTER_REGNUM): Change to 111.
+       (enum reg_class): Remove the SPE_ACC and SPEFSCR registers.
+       (REG_CLASS_NAMES): Ditto.
+       (REG_CLASS_CONTENTS): Delete the SPE_ACC and SPEFSCR registers.
+       (REGISTER_NAMES): Ditto.
+       (ADDITIONAL_REG_NAMES): Ditto.
+       (rs6000_reg_names): Ditto.
+       * config/rs6000/rs6000.md: Renumber some register number
+       define_constants.
+
 2017-06-07  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high

diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 2422f259447f3bf879642206a10cacb6476a531b..90fc757532aa56463c8136b6b358c686c234a2f8 100644 (file)
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -192,7 +192,6 @@ extern int darwin_emit_branch_islands;
     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",             \
     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",             \
     "vrsave", "vscr",                                                  \
-    "spe_acc", "spefscr",                                               \
     "sfp",                                                             \
     "tfhar", "tfiar", "texasr"                                         \
 }

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 598ed9d90e18e5f12033a942514373331952d2df..d369e1ad954d9a344fed2dcd15cd39e50ab1c6be 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -437,8 +437,6 @@ enum rs6000_reg_type {
   FPR_REG_TYPE,
   SPR_REG_TYPE,
   CR_REG_TYPE,
-  SPE_ACC_TYPE,
-  SPEFSCR_REG_TYPE
 };
 
 /* Map register class to register type.  */
@@ -1502,8 +1500,6 @@ char rs6000_reg_names[][8] =
       "16", "17", "18", "19", "20", "21", "22", "23",
       "24", "25", "26", "27", "28", "29", "30", "31",
       "vrsave", "vscr",
-      /* SPE registers.  */
-      "spe_acc", "spefscr",
       /* Soft frame pointer.  */
       "sfp",
       /* HTM SPR registers.  */
@@ -1530,8 +1526,6 @@ static const char alt_reg_names[][8] =
   "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
   "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
   "vrsave", "vscr",
-  /* SPE registers.  */
-  "spe_acc", "spefscr",
   /* Soft frame pointer.  */
   "sfp",
   /* HTM SPR registers.  */
@@ -2514,8 +2508,6 @@ rs6000_debug_reg_global (void)
   rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
   rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
   rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
-  rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
-  rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
 
   fputs ("\nVirtual/stack/frame registers:\n", stderr);
   for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
@@ -3024,8 +3016,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   rs6000_regno_regclass[CA_REGNO] = NO_REGS;
   rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
   rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
-  rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
-  rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
   rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
   rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
   rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
@@ -3048,8 +3038,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
   reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
   reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
-  reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;
-  reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;
 
   if (TARGET_VSX)
     {
@@ -37481,10 +37469,6 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format)
     return 356;
   if (regno == VSCR_REGNO)
     return 67;
-  if (regno == SPE_ACC_REGNO)
-    return 99;
-  if (regno == SPEFSCR_REGNO)
-    return 612;
 #endif
   return regno;
 }

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index a154c5daae6beb1cd161a8b4c443f48e3d23b266..edfa54603f775a7c0818ea28963ad285ec4ecf2e 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1017,7 +1017,7 @@ enum data_align { align_abi, align_opt, align_both };
 
    The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS.  */
 
-#define FIRST_PSEUDO_REGISTER 117
+#define FIRST_PSEUDO_REGISTER 115
 
 /* This must be included for pre gcc 3.0 glibc compatibility.  */
 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
@@ -1056,7 +1056,7 @@ enum data_align { align_abi, align_opt, align_both };
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    1, 1                                                   \
-   , 1, 1, 1, 1, 1, 1                             \
+   , 1, 1, 1, 1                                           \
 }
 
 /* 1 for registers not available across function calls.
@@ -1076,7 +1076,7 @@ enum data_align { align_abi, align_opt, align_both };
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    1, 1                                                   \
-   , 1, 1, 1, 1, 1, 1                             \
+   , 1, 1, 1, 1                                           \
 }
 
 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -1095,7 +1095,7 @@ enum data_align { align_abi, align_opt, align_both };
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
    0, 0                                                   \
-   , 0, 0, 0, 0, 0, 0                             \
+   , 0, 0, 0, 0                                           \
 }
 
 #define TOTAL_ALTIVEC_REGS     (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -1133,7 +1133,6 @@ enum data_align { align_abi, align_opt, align_both };
        v19 - v14       (not saved or used for anything)
        v31 - v20       (saved; order given to save least number)
        vrsave, vscr    (fixed)
-       spe_acc, spefscr (fixed)
        sfp             (fixed)
        tfhar           (fixed)
        tfiar           (fixed)
@@ -1179,7 +1178,7 @@ enum data_align { align_abi, align_opt, align_both };
    96, 95, 94, 93, 92, 91,                                     \
    108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97,    \
    109, 110,                                                   \
-   111, 112, 113, 114, 115, 116                                        \
+   111, 112, 113, 114                                          \
 }
 
 /* True if register is floating-point.  */
@@ -1351,7 +1350,7 @@ enum data_align { align_abi, align_opt, align_both };
 #define HARD_FRAME_POINTER_REGNUM 31
 
 /* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 113
+#define FRAME_POINTER_REGNUM 111
 
 /* Base register for access to arguments of the function.  */
 #define ARG_POINTER_REGNUM 67
@@ -1404,8 +1403,6 @@ enum reg_class
   VSX_REGS,
   VRSAVE_REGS,
   VSCR_REGS,
-  SPE_ACC_REGS,
-  SPEFSCR_REGS,
   SPR_REGS,
   NON_SPECIAL_REGS,
   LINK_REGS,
@@ -1435,8 +1432,6 @@ enum reg_class
   "VSX_REGS",                                                          \
   "VRSAVE_REGS",                                                       \
   "VSCR_REGS",                                                         \
-  "SPE_ACC_REGS",                                                       \
-  "SPEFSCR_REGS",                                                       \
   "SPR_REGS",                                                          \
   "NON_SPECIAL_REGS",                                                  \
   "LINK_REGS",                                                         \
@@ -1460,9 +1455,9 @@ enum reg_class
   /* NO_REGS.  */                                                      \
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },                  \
   /* BASE_REGS.  */                                                    \
-  { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 },                  \
+  { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 },                  \
   /* GENERAL_REGS.  */                                                 \
-  { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 },                  \
+  { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 },                  \
   /* FLOAT_REGS.  */                                                   \
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 },                  \
   /* ALTIVEC_REGS.  */                                                 \
@@ -1473,14 +1468,10 @@ enum reg_class
   { 0x00000000, 0x00000000, 0x00000000, 0x00002000 },                  \
   /* VSCR_REGS.  */                                                    \
   { 0x00000000, 0x00000000, 0x00000000, 0x00004000 },                  \
-  /* SPE_ACC_REGS.  */                                                 \
-  { 0x00000000, 0x00000000, 0x00000000, 0x00008000 },                  \
-  /* SPEFSCR_REGS.  */                                                 \
-  { 0x00000000, 0x00000000, 0x00000000, 0x00010000 },                  \
   /* SPR_REGS.  */                                                     \
-  { 0x00000000, 0x00000000, 0x00000000, 0x00040000 },                  \
+  { 0x00000000, 0x00000000, 0x00000000, 0x00010000 },                  \
   /* NON_SPECIAL_REGS.  */                                             \
-  { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 },                  \
+  { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 },                  \
   /* LINK_REGS.  */                                                    \
   { 0x00000000, 0x00000000, 0x00000002, 0x00000000 },                  \
   /* CTR_REGS.  */                                                     \
@@ -1490,17 +1481,17 @@ enum reg_class
   /* SPECIAL_REGS.  */                                                 \
   { 0x00000000, 0x00000000, 0x00000006, 0x00002000 },                  \
   /* SPEC_OR_GEN_REGS.  */                                             \
-  { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 },                  \
+  { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 },                  \
   /* CR0_REGS.  */                                                     \
   { 0x00000000, 0x00000000, 0x00000010, 0x00000000 },                  \
   /* CR_REGS.  */                                                      \
   { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 },                  \
   /* NON_FLOAT_REGS.  */                                               \
-  { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 },                  \
+  { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 },                  \
   /* CA_REGS.  */                                                      \
   { 0x00000000, 0x00000000, 0x00001000, 0x00000000 },                  \
   /* ALL_REGS.  */                                                     \
-  { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff }                   \
+  { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff }                   \
 }
 
 /* The same information, inverted:
@@ -2429,12 +2420,10 @@ extern char rs6000_reg_names[][8];      /* register names (0 vs. %r0).  */
   &rs6000_reg_names[108][0],   /* v31  */                              \
   &rs6000_reg_names[109][0],   /* vrsave  */                           \
   &rs6000_reg_names[110][0],   /* vscr  */                             \
-  &rs6000_reg_names[111][0],   /* spe_acc */                           \
-  &rs6000_reg_names[112][0],   /* spefscr */                           \
-  &rs6000_reg_names[113][0],   /* sfp  */                              \
-  &rs6000_reg_names[114][0],   /* tfhar  */                            \
-  &rs6000_reg_names[115][0],   /* tfiar  */                            \
-  &rs6000_reg_names[116][0],   /* texasr  */                           \
+  &rs6000_reg_names[111][0],   /* sfp  */                              \
+  &rs6000_reg_names[112][0],   /* tfhar  */                            \
+  &rs6000_reg_names[113][0],   /* tfiar  */                            \
+  &rs6000_reg_names[114][0],   /* texasr  */                           \
 }
 
 /* Table of additional register names to use in user input.  */
@@ -2465,7 +2454,6 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"v24",  101},{"v25",  102},{"v26",  103},{"v27",  104},      \
   {"v28",  105},{"v29",  106},{"v30",  107},{"v31",  108},      \
   {"vrsave", 109}, {"vscr", 110},                              \
-  {"spe_acc", 111}, {"spefscr", 112},                          \
   /* no additional names for: lr, ctr, ap */                   \
   {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71},      \
   {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75},      \
@@ -2490,7 +2478,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104},      \
   {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108},     \
   /* Transactional Memory Facility (HTM) Registers.  */                \
-  {"tfhar",  114}, {"tfiar",  115}, {"texasr",  116},          \
+  {"tfhar",  112}, {"tfiar",  113}, {"texasr",  114},          \
 }
 
 /* This is how to output an element of a case-vector that is relative.  */

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9cf761cf8ba001936884058446df86564090d270..d0120d1cfa5f42ed30dfada816c5c0115184143b 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -50,12 +50,10 @@
    (LAST_ALTIVEC_REGNO         108)
    (VRSAVE_REGNO               109)
    (VSCR_REGNO                 110)
-   (SPE_ACC_REGNO              111)
-   (SPEFSCR_REGNO              112)
-   (FRAME_POINTER_REGNUM       113)
-   (TFHAR_REGNO                        114)
-   (TFIAR_REGNO                        115)
-   (TEXASR_REGNO               116)
+   (FRAME_POINTER_REGNUM       111)
+   (TFHAR_REGNO                        112)
+   (TFIAR_REGNO                        113)
+   (TEXASR_REGNO               114)
   ])
 
 ;;