DONE;
})
-(define_expand "vec_setv4sf"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:SF 1 "register_operand" "")
+(define_expand "vec_set<mode>"
+ [(match_operand:SSEMODE 0 "register_operand" "")
+ (match_operand:<ssescalarmode> 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
"TARGET_SSE"
{
[(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
(set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
-(define_expand "vec_setv2df"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- ix86_expand_vector_set (false, operands[0], operands[1],
- INTVAL (operands[2]));
- DONE;
-})
-
(define_expand "vec_extractv2df"
[(match_operand:DF 0 "register_operand" "")
(match_operand:V2DF 1 "register_operand" "")
[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,ssemov")
(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
-(define_expand "vec_setv2di"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- ix86_expand_vector_set (false, operands[0], operands[1],
- INTVAL (operands[2]));
- DONE;
-})
-
(define_expand "vec_extractv2di"
[(match_operand:DI 0 "register_operand" "")
(match_operand:V2DI 1 "register_operand" "")
DONE;
})
-(define_expand "vec_setv4si"
- [(match_operand:V4SI 0 "register_operand" "")
- (match_operand:SI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- ix86_expand_vector_set (false, operands[0], operands[1],
- INTVAL (operands[2]));
- DONE;
-})
-
(define_expand "vec_extractv4si"
[(match_operand:SI 0 "register_operand" "")
(match_operand:V4SI 1 "register_operand" "")
DONE;
})
-(define_expand "vec_setv8hi"
- [(match_operand:V8HI 0 "register_operand" "")
- (match_operand:HI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- ix86_expand_vector_set (false, operands[0], operands[1],
- INTVAL (operands[2]));
- DONE;
-})
-
(define_expand "vec_extractv8hi"
[(match_operand:HI 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")
DONE;
})
-(define_expand "vec_setv16qi"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:QI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- ix86_expand_vector_set (false, operands[0], operands[1],
- INTVAL (operands[2]));
- DONE;
-})
-
(define_expand "vec_extractv16qi"
[(match_operand:QI 0 "register_operand" "")
(match_operand:V16QI 1 "register_operand" "")