back.rtlil: don't emit connections to zero width ports.

Fixes #335.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index f6836872fc475564ba238b0a0dfe4028b7b16b4c..90c5ed9a1c7db8a0b0e483d8a2616b8f03834501 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -880,7 +880,8 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                 if not isinstance(subfragment, ir.Instance):
                     for signal in value._rhs_signals():
                         compiler_state.resolve_curr(signal, prefix=sub_name)
-                sub_ports[port] = rhs_compiler(value)
+                if len(value) > 0:
+                    sub_ports[port] = rhs_compiler(value)
 
             module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params,
                         attrs=subfragment.attrs)