read_verilog -defer should still populate module attributes
authorEddie Hung <eddie@fpgeh.com>
Thu, 29 Aug 2019 02:59:09 +0000 (19:59 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 29 Aug 2019 02:59:09 +0000 (19:59 -0700)
frontends/ast/ast.cc

index 82283fb5bcc9a752217135012bcb50293928d14a..6a91c418b8135bc63b05a8b00a4c397b8150767a 100644 (file)
@@ -1073,11 +1073,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 
                ignoreThisSignalsInInitial = RTLIL::SigSpec();
 
-               for (auto &attr : ast->attributes) {
-                       if (attr.second->type != AST_CONSTANT)
-                               log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
-                       current_module->attributes[attr.first] = attr.second->asAttrConst();
-               }
                for (size_t i = 0; i < ast->children.size(); i++) {
                        AstNode *node = ast->children[i];
                        if (node->type == AST_WIRE || node->type == AST_MEMORY)
@@ -1100,6 +1095,12 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
                ignoreThisSignalsInInitial = RTLIL::SigSpec();
        }
 
+       for (auto &attr : ast->attributes) {
+               if (attr.second->type != AST_CONSTANT)
+                       log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+               current_module->attributes[attr.first] = attr.second->asAttrConst();
+       }
+
        if (ast->type == AST_INTERFACE)
                current_module->set_bool_attribute("\\is_interface");
        current_module->ast = ast_before_simplify;