inorder: no dep. tracking for zero reg

this causes forwarding a bad value register value

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index c7eb35b475bdd9e26a599c74745ad78ede67de81..03c44ea86aa5fbf6940304e6b96144ffbe9b3a8c 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1312,7 +1312,6 @@ InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
     lastCommittedPC[tid] = comm_pc;
     TheISA::advancePC(comm_pc, inst->staticInst);
     pcState(comm_pc, tid);
-    DPRINTF(InOrderGraduation, "Precise State PC = %s\n", pcState(tid));
 
     //@todo: may be unnecessary with new-ISA-specific branch handling code
     if (inst->isControl()) {

diff --git a/src/cpu/inorder/reg_dep_map.cc b/src/cpu/inorder/reg_dep_map.cc
index 9898de43d9b475f66fe8d4e22a71fac5e6235af5..075c31208bf9616c98db7b34bc12c47bf197277c 100644 (file)
--- a/src/cpu/inorder/reg_dep_map.cc
+++ b/src/cpu/inorder/reg_dep_map.cc
@@ -103,6 +103,14 @@ RegDepMap::insert(DynInstPtr inst)
                 inst->seqNum, i, raw_idx, flat_idx);
 
         inst->flattenDestReg(i, flat_idx);
+
+        if (flat_idx == TheISA::ZeroReg) {
+            DPRINTF(IntRegs, "[sn:%i]: Ignoring Insert-Dependency tracking for "
+                    "ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
+                    flat_idx);
+            continue;
+        }
+
         insert(reg_type, flat_idx, inst);
     }
 }
@@ -134,8 +142,17 @@ RegDepMap::remove(DynInstPtr inst)
 
 
         for (int i = 0; i < dest_regs; i++) {
+            RegIndex flat_idx = inst->flattenedDestRegIdx(i);
+
+            if (flat_idx == TheISA::ZeroReg) {
+                DPRINTF(IntRegs, "[sn:%i]: Ignoring Remove-Dependency tracking for "
+                        "ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
+                        flat_idx);
+                continue;
+            }
+
             InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
-            remove(reg_type, inst->flattenedDestRegIdx(i), inst);
+            remove(reg_type, flat_idx, inst);
         }
     }
 }

diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index 0ab9d96c7225053a1d1283d124982076a5f70b23..1ba5c204acf8ecc888837dc8f36e577b55c4aa06 100644 (file)
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -62,6 +62,10 @@ DecodeUnit::execute(int slot_num)
         {
             assert(!inst->staticInst->isMacroop());
 
+            DPRINTF(Decode,"Decoded instruction [sn:%i]: %s : 0x%x\n",
+                    inst->seqNum, inst->instName(),
+                    inst->staticInst->machInst);
+
             inst->setBackSked(cpu->createBackEndSked(inst));
 
             if (inst->backSked != NULL) {

diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc
index 9c17db945ae46f1b7491cf0eb4b71dd2cc1d9bc2..641d7b5ad00f5d915c56c63d5613fbe29ab4b42c 100644 (file)
--- a/src/cpu/inorder/resources/graduation_unit.cc
+++ b/src/cpu/inorder/resources/graduation_unit.cc
@@ -78,8 +78,8 @@ GraduationUnit::execute(int slot_num)
             }
 
             DPRINTF(InOrderGraduation,
-                    "[tid:%i] Graduating instruction %s [sn:%i].\n",
-                    tid, inst->instName(), inst->seqNum);
+                    "[tid:%i]:[sn:%i]: Graduating instruction %s.\n",
+                    tid, inst->seqNum, inst->instName());
 
             // Release Non-Speculative "Block" on instructions that could not
             // execute because there was a non-speculative inst. active.

diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index 392239d42a5b50590f0596fe5a721e2e0e114b44..1adee09db9b7dcf22ac101cbeef1fbb4e10251d3 100644 (file)
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -181,9 +181,16 @@ UseDefUnit::execute(int slot_idx)
             RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
             inst->flattenSrcReg(ud_idx, flat_idx);
             
-            DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
-                    "register idx %i (reg #%i, flat#%i).\n",
-                    tid, seq_num, ud_idx, reg_idx, flat_idx);
+            if (flat_idx == TheISA::ZeroReg) {
+                DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Ignoring Reading of ISA-ZeroReg "
+                        "(Int. Reg %i).\n", tid, inst->seqNum, flat_idx);
+                ud_req->done();
+                return;
+            } else {
+                DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
+                        "register idx %i (reg #%i, flat#%i).\n",
+                        tid, seq_num, ud_idx, reg_idx, flat_idx);
+            }
 
             if (regDepMap[tid]->canRead(reg_type, flat_idx, inst)) {
                 switch (reg_type)
@@ -324,6 +331,13 @@ UseDefUnit::execute(int slot_idx)
             RegIndex reg_idx = inst->_destRegIdx[ud_idx];
             RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
 
+            if (flat_idx == TheISA::ZeroReg) {
+                DPRINTF(IntRegs, "[tid:%i]: Ignoring Writing of ISA-ZeroReg "
+                        "(Int. Reg %i)\n", tid, flat_idx);
+                ud_req->done();
+                return;
+            }
+
             if (regDepMap[tid]->canWrite(reg_type, flat_idx, inst)) {
                 DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Flattening register idx %i "
                         "(%i) and Attempting to write to Register File.\n",