radv: remove radeon_surf_level::dcc_enabled

Like radeonsi; replace with radeon_surf::num_dcc_levels.

Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e661d2207383276fa339ea079ec3d9d5aa90cb14..88aaae738e581591eb36b4de9f1de66355001877 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2773,7 +2773,7 @@ radv_initialise_color_surface(struct radv_device *device,
            !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
                cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
 
-       if (iview->image->surface.dcc_size && level_info->dcc_enabled)
+       if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
                cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
 
        if (device->physical_device->rad_info.chip_class >= VI) {

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index a1598fcbb7b2d03da8d03e723ecbe161dfe75096..842f2919ca985978d298cade592005a47649c5ab 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -212,7 +212,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                                                             is_stencil));
        state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
 
-       if (image->surface.dcc_size && image->surface.level[first_level].dcc_enabled) {
+       if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
                state[6] |= S_008F28_COMPRESSION_EN(1);
                state[7] = (gpu_address +
                            image->dcc_offset +

diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index fca6005ea176072338797d0e197467aec8a043ae..44e64022a0d6794a0b435383194baae22c4995f1 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -315,7 +315,7 @@ static void radv_pick_resolve_method_images(struct radv_image *src_image,
 
 {
        if (dest_image->surface.micro_tile_mode != src_image->surface.micro_tile_mode) {
-               if (dest_image->surface.level[0].dcc_enabled)
+               if (dest_image->surface.num_dcc_levels > 0)
                        *method = RESOLVE_FRAGMENT;
                else
                        *method = RESOLVE_COMPUTE;

diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index df582d8c610129e2673cc21129333dd463c5390f..365ff1160fdeb99cb7cf63ecf1a7588d168c5a41 100644 (file)
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -171,7 +171,6 @@ struct radeon_surf_level {
        uint32_t                    nblk_y;
        uint32_t                    nblk_z;
        uint32_t                    mode;
-       bool                        dcc_enabled;
        uint64_t                    dcc_offset;
        uint64_t                    dcc_fast_clear_size;
 };
@@ -185,6 +184,8 @@ struct radeon_surf {
        uint32_t                    bpe;
        uint32_t                    flags;
 
+       unsigned                    num_dcc_levels:4;
+
        /* These are return values. Some of them can be set by the caller, but
         * they will be treated as hints (e.g. bankw, bankh) and might be
         * changed by the calculator.

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index f8e22da16b6afef80ec41b432dc989691113e268..ab1f9520b44f03989f0443edc47f4f30a85ffa13 100644 (file)
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -233,7 +233,6 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 
        /* Clear DCC fields at the beginning. */
        surf_level->dcc_offset = 0;
-       surf_level->dcc_enabled = false;
 
        /* The previous level's flag tells us if we can use DCC for this level. */
        if (AddrSurfInfoIn->flags.dccCompatible &&
@@ -251,7 +250,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
                if (ret == ADDR_OK) {
                        surf_level->dcc_offset = surf->dcc_size;
                        surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
-                       surf_level->dcc_enabled = true;
+                       surf->num_dcc_levels = level + 1;
                        surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
                        surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
                }
@@ -476,6 +475,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
        }
 
        surf->bo_size = 0;
+       surf->num_dcc_levels = 0;
        surf->dcc_size = 0;
        surf->dcc_alignment = 1;
        surf->htile_size = surf->htile_slice_size = 0;