* app.c: Remove trailing white spaces.
* as.c: Likewise.
* as.h: Likewise.
* cond.c: Likewise.
* dw2gencfi.c: Likewise.
* dwarf2dbg.h: Likewise.
* ecoff.c: Likewise.
* input-file.c: Likewise.
* itbl-lex.h: Likewise.
* output-file.c: Likewise.
* read.c: Likewise.
* sb.c: Likewise.
* subsegs.c: Likewise.
* symbols.c: Likewise.
* write.c: Likewise.
* config/tc-i386.c: Likewise.
* doc/Makefile.am: Likewise.
* doc/Makefile.in: Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-alpha.texi: Likewise.
* doc/c-arc.texi: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-avr.texi: Likewise.
* doc/c-bfin.texi: Likewise.
* doc/c-cr16.texi: Likewise.
* doc/c-d10v.texi: Likewise.
* doc/c-d30v.texi: Likewise.
* doc/c-h8300.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-i860.texi: Likewise.
* doc/c-m32c.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68hc11.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-microblaze.texi: Likewise.
* doc/c-mips.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-mt.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-score.texi: Likewise.
* doc/c-sh.texi: Likewise.
* doc/c-sh64.texi: Likewise.
* doc/c-tic54x.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xc16x.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* doc/c-z80.texi: Likewise.
* doc/internals.texi: Likewise.
+2013-01-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * app.c: Remove trailing white spaces.
+ * as.c: Likewise.
+ * as.h: Likewise.
+ * cond.c: Likewise.
+ * dw2gencfi.c: Likewise.
+ * dwarf2dbg.h: Likewise.
+ * ecoff.c: Likewise.
+ * input-file.c: Likewise.
+ * itbl-lex.h: Likewise.
+ * output-file.c: Likewise.
+ * read.c: Likewise.
+ * sb.c: Likewise.
+ * subsegs.c: Likewise.
+ * symbols.c: Likewise.
+ * write.c: Likewise.
+ * config/tc-i386.c: Likewise.
+ * doc/Makefile.am: Likewise.
+ * doc/Makefile.in: Likewise.
+ * doc/c-aarch64.texi: Likewise.
+ * doc/c-alpha.texi: Likewise.
+ * doc/c-arc.texi: Likewise.
+ * doc/c-arm.texi: Likewise.
+ * doc/c-avr.texi: Likewise.
+ * doc/c-bfin.texi: Likewise.
+ * doc/c-cr16.texi: Likewise.
+ * doc/c-d10v.texi: Likewise.
+ * doc/c-d30v.texi: Likewise.
+ * doc/c-h8300.texi: Likewise.
+ * doc/c-hppa.texi: Likewise.
+ * doc/c-i370.texi: Likewise.
+ * doc/c-i386.texi: Likewise.
+ * doc/c-i860.texi: Likewise.
+ * doc/c-m32c.texi: Likewise.
+ * doc/c-m32r.texi: Likewise.
+ * doc/c-m68hc11.texi: Likewise.
+ * doc/c-m68k.texi: Likewise.
+ * doc/c-microblaze.texi: Likewise.
+ * doc/c-mips.texi: Likewise.
+ * doc/c-msp430.texi: Likewise.
+ * doc/c-mt.texi: Likewise.
+ * doc/c-s390.texi: Likewise.
+ * doc/c-score.texi: Likewise.
+ * doc/c-sh.texi: Likewise.
+ * doc/c-sh64.texi: Likewise.
+ * doc/c-tic54x.texi: Likewise.
+ * doc/c-tic6x.texi: Likewise.
+ * doc/c-v850.texi: Likewise.
+ * doc/c-xc16x.texi: Likewise.
+ * doc/c-xgate.texi: Likewise.
+ * doc/c-xtensa.texi: Likewise.
+ * doc/c-z80.texi: Likewise.
+ * doc/internals.texi: Likewise.
+
2013-01-10 Roland McGrath <mcgrathr@google.com>
* hash.c (hash_new_sized): Make it global.
case 16:
/* We have seen an 'a' at the start of a symbol, look for an 'f'. */
ch = GET ();
- if (ch == 'f' || ch == 'F')
+ if (ch == 'f' || ch == 'F')
{
state = 17;
PUT (ch);
#ifdef TC_Z80
/* "af'" is a symbol containing '\''. */
- if (state == 3 && (ch == 'a' || ch == 'A'))
+ if (state == 3 && (ch == 'a' || ch == 'A'))
{
state = 16;
PUT (ch);
ch = GET ();
- if (ch == 'f' || ch == 'F')
+ if (ch == 'f' || ch == 'F')
{
state = 17;
PUT (ch);
Understands command arguments.
Has a few routines that don't fit in other modules because they
are shared.
-
+
bugs
-
+
: initialisers
Since no-one else says they will support them in future: I
don't support them now. */
--listing-cont-lines set the maximum number of continuation lines used\n\
for the output data column of the listing\n"));
fprintf (stream, _("\
- @FILE read options from FILE\n"));
+ @FILE read options from FILE\n"));
md_show_usage (stream);
/* When you add options here, check that they do
not collide with OPTION_MD_BASE. See as.h. */
};
-
+
static const struct option std_longopts[] =
{
/* Note: commas are placed at the start of the line rather than
gnustack = subseg_new (".note.GNU-stack", 0);
bfd_set_section_flags (stdoutput, gnustack,
SEC_READONLY | (flag_execstack ? SEC_CODE : 0));
-
+
}
#endif
assembly debugging or on behalf of the compiler, emit it now. */
dwarf2_finish ();
- /* If we constructed dwarf2 .eh_frame info, either via .cfi
+ /* If we constructed dwarf2 .eh_frame info, either via .cfi
directives from the user or by the backend, emit it now. */
cfi_finish ();
#ifndef GAS
#define GAS 1
/* I think this stuff is largely out of date. xoxorich.
-
+
CAPITALISED names are #defined.
"lowercaseH" is #defined if "lowercase.h" has been #include-d.
"lowercaseT" is a typedef of "lowercase" objects.
"lowercaseP" is type "pointer to object of type 'lowercase'".
"lowercaseS" is typedef struct ... lowercaseS.
-
+
#define DEBUG to enable all the "know" assertion tests.
#define SUSPECT when debugging hash code.
#define COMMON as "extern" for all modules except one, where you #define
*input_line_pointer = c;
initialize_cframe (&cframe);
-
+
if (cframe.dead_tree)
cframe.ignoring = 1;
else
struct conditional_frame cframe;
initialize_cframe (&cframe);
-
+
if (cframe.dead_tree)
cframe.ignoring = 1;
else
input string, minus the `@SECREL32' into a malloc'd buffer for
parsing by the calling routine. Return this buffer, and if ADJUST
is non-null set it to the length of the string we removed from the
- input line. Otherwise return NULL.
-
+ input line. Otherwise return NULL.
+
This function is copied from the ELF version above adjusted for PE targets. */
static char *
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
man_MANS = as.1
-info_TEXINFOS = as.texinfo
+info_TEXINFOS = as.texinfo
as_TEXINFOS = asconfig.texi $(CPU_DOCS)
AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
--release="binutils-$(VERSION)" --section=1
man_MANS = as.1
-info_TEXINFOS = as.texinfo
+info_TEXINFOS = as.texinfo
as_TEXINFOS = asconfig.texi $(CPU_DOCS)
AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
fi; \
rm -rf $$backupdir; exit $$rc
-as.dvi: as.texinfo $(as_TEXINFOS)
+as.dvi: as.texinfo $(as_TEXINFOS)
TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
$(TEXI2DVI) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
-as.pdf: as.texinfo $(as_TEXINFOS)
+as.pdf: as.texinfo $(as_TEXINFOS)
TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
$(TEXI2PDF) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
-as.html: as.texinfo $(as_TEXINFOS)
+as.html: as.texinfo $(as_TEXINFOS)
rm -rf $(@:.html=.htp)
if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-o $(@:.html=.htp) `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \
instructions can be generated by prefixing the label with
@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
-For example to use 33-bit (+/-4GB) pc-relative addressing to
+For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of @var{foo} into x0:
@smallexample
@cindex opcodes for AArch64
@code{@value{AS}} implements all the standard AArch64 opcodes. It also
implements several pseudo opcodes, including several synthetic load
-instructions.
+instructions.
@table @code
the assembler may either expand the instruction as a macro or issue an
error message. This option is equivalent to the @code{.arch} directive.
-The following processor names are recognized:
+The following processor names are recognized:
@code{21064},
@code{21064a},
@code{21066},
@cindex relocations, Alpha
Some of these relocations are available for ECOFF, but mostly
-only for ELF. They are modeled after the relocation format
+only for ELF. They are modeled after the relocation format
introduced in Digital Unix 4.0, but there are additions.
The format is @samp{!@var{tag}} or @samp{!@var{tag}!@var{number}}
@item !lituse_tlsgd!@var{N}
Used with a register branch format instruction to indicate that the
-literal is the call to @code{__tls_get_addr} used to compute the
+literal is the call to @code{__tls_get_addr} used to compute the
address of the thread-local storage variable whose descriptor was
loaded with @code{!tlsgd!@var{N}}.
@item !lituse_tlsldm!@var{N}
Used with a register branch format instruction to indicate that the
-literal is the call to @code{__tls_get_addr} used to compute the
+literal is the call to @code{__tls_get_addr} used to compute the
address of the base of the thread-local storage block for the current
module. The descriptor for the module must have been loaded with
@code{!tlsldm!@var{N}}.
address, a-la the @code{ldgp} macro. The source register for the
@code{ldah} instruction must contain the address of the @code{ldah}
instruction. There must be exactly one @code{lda} instruction paired
-with the @code{ldah} instruction, though it may appear anywhere in
+with the @code{ldah} instruction, though it may appear anywhere in
the instruction stream. The immediate operands must be zero.
@example
the procedure vector during relaxation.
@item .usepv @var{function}, @var{which}
-Used to indicate the use of the @code{$27} register, similar to
-@code{.prologue}, but without the other semantics of needing to
+Used to indicate the use of the @code{$27} register, similar to
+@code{.prologue}, but without the other semantics of needing to
be inside an open @code{.ent}/@code{.end} block.
The @var{which} argument should be either @code{no}, indicating that
new auxiallry register. The second parameter is the @var{address} of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the @var{mode} in which the
-register can be operated is and it can be one of:
+register can be operated is and it can be one of:
@table @code
-@item r (readonly)
+@item r (readonly)
@item w (write only)
@item r|w (read or write)
@end table
@smallexample
.extCondCode is_busy,0x14
-
+
add.is_busy r1,r2,r3
bis_busy _main
@end smallexample
@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
Specifies an extension core register @var{name} for the application.
This allows a register @var{name} with a valid @var{regnum} between 0
-and 60, with the following as valid values for @var{mode}
+and 60, with the following as valid values for @var{mode}
@table @samp
-@item @emph{r} (readonly)
+@item @emph{r} (readonly)
@item @emph{w} (write only)
@item @emph{r|w} (read or write)
@end table
@table @bullet
@item @var{name}
-Name of the extension instruction
+Name of the extension instruction
@item @var{opcode}
Opcode to be used. (Bits 27:31 in the encoding). Valid values
@item @var{suffixclass}
Determines the kinds of suffixes to be allowed. Valid values are
-@code{SUFFIX_NONE}, @code{SUFFIX_COND},
+@code{SUFFIX_NONE}, @code{SUFFIX_COND},
@code{SUFFIX_FLAG} which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
@table @code
@item @code{SYNTAX_2OP}:
-2 Operand Instruction
+2 Operand Instruction
@item @code{SYNTAX_3OP}:
-3 Operand Instruction
+3 Operand Instruction
@end table
In addition there could be modifiers for the syntax class as described
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
-to set the flags using specific instructions and not retain results.
+to set the flags using specific instructions and not retain results.
@item @code{OP1_IMM_IMPLIED}:
Modifies syntax class SYNTAX_20P, it specifies that there is an
syntax. For example, if the source code contains an instruction like:
@smallexample
-inst r1,r2
+inst r1,r2
@end smallexample
it really means that the first argument is an implied immediate (that
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
-@end itemize
+@end itemize
@end table
For example, defining 64-bit multiplier with immediate operands:
The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
-first operand is an immediate. (Equivalent to discarding the result
+first operand is an immediate. (Equivalent to discarding the result
of the operation).
@smallexample
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
-recognized:
+recognized:
@code{arm1},
@code{arm2},
@code{arm250},
@code{i80200} (Intel XScale processor)
@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
-@code{xscale}.
+@code{xscale}.
The special name @code{all} may be used to allow the
assembler to accept instructions valid for any ARM processor.
-In addition to the basic instruction set, the assembler can be told to
-accept various extension mnemonics that extend the processor using the
+In addition to the basic instruction set, the assembler can be told to
+accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
-is equivalent to specifying @code{-mcpu=ep9312}.
+is equivalent to specifying @code{-mcpu=ep9312}.
-Multiple extensions may be specified, separated by a @code{+}. The
+Multiple extensions may be specified, separated by a @code{+}. The
extensions should be specified in ascending alphabetical order.
-Some extensions may be restricted to particular architectures; this is
+Some extensions may be restricted to particular architectures; this is
documented in the list of extensions below.
-Extension mnemonics may also be removed from those the assembler accepts.
-This is done be prepending @code{no} to the option that adds the extension.
-Extensions that are removed should be listed after all extensions which have
-been added, again in ascending alphabetical order. For example,
+Extension mnemonics may also be removed from those the assembler accepts.
+This is done be prepending @code{no} to the option that adds the extension.
+Extensions that are removed should be listed after all extensions which have
+been added, again in ascending alphabetical order. For example,
@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
@code{os} (Operating System for v6M architecture),
@code{sec} (Security Extensions for v6K and v7-A architectures),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
-@code{virt} (Virtualization Extensions for v7-A architecture, implies
+@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
and
@code{xscale}.
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
-will not execute on the target architecture. The following architecture
-names are recognized:
+will not execute on the target architecture. The following architecture
+names are recognized:
@code{armv1},
@code{armv2},
@code{armv2a},
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
-an instruction which will not execute on the target floating point unit.
+an instruction which will not execute on the target floating point unit.
The following format options are recognized:
@code{softfpa},
@code{fpe},
also affects the way in which the @code{.double} assembler directive behaves
when assembling little-endian code.
-The default is dependent on the processor selected. For Architecture 5 or
-later, the default is to assembler for VFP instructions; for earlier
+The default is dependent on the processor selected. For Architecture 5 or
+later, the default is to assembler for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
@cindex @code{-mthumb} command line option, ARM
@item -mthumb
This option specifies that the assembler should start assembling Thumb
-instructions; that is, it should behave as though the file starts with a
+instructions; that is, it should behave as though the file starts with a
@code{.code 16} directive.
@cindex @code{-mthumb-interwork} command line option, ARM
@cindex @code{-matpcs} command line option, ARM
@item -matpcs
-This option specifies that the output generated by the assembler should
+This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
Select the target architecture. Valid values for @var{name} are the same as
for the @option{-march} commandline option.
-Specifying @code{.arch} clears any previously selected architecture
+Specifying @code{.arch} clears any previously selected architecture
extensions.
@cindex @code{.arch_extension} directive, ARM
@item .arch_extension @var{name}
-Add or remove an architecture extension to the target architecture. Valid
-values for @var{name} are the same as those accepted as architectural
+Add or remove an architecture extension to the target architecture. Valid
+values for @var{name} are the same as those accepted as architectural
extensions by the @option{-mcpu} commandline option.
@code{.arch_extension} may be used multiple times to add or remove extensions
Select the target processor. Valid values for @var{name} are the same as
for the @option{-mcpu} commandline option.
-Specifying @code{.cpu} clears any previously selected architecture
+Specifying @code{.cpu} clears any previously selected architecture
extensions.
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
@code{number, "string"} depending on the tag.
Note - the following legacy values are also accepted by @var{tag}:
-@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
+@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
@cindex @code{.even} directive, ARM
@cindex opcodes for ARM
@code{@value{AS}} implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
-instructions.
+instructions.
@table @code
nothing. Currently it will evaluate to MOV r0, r0.
@cindex @code{LDR reg,=<label>} pseudo op, ARM
-@item LDR
+@item LDR
@smallexample
ldr <register> , = <expression>
@end smallexample
will not make use of the literal pool.
@cindex @code{ADRL reg,<label>} pseudo op, ARM
-@item ADRL
+@item ADRL
@smallexample
adrl <register> <label>
@end smallexample
@verbatim
void callee (int *);
-int
-caller ()
+int
+caller ()
{
int i;
callee (&i);
- return i;
+ return i;
}
@end verbatim
op appears immediately before the first instruction of the function
while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
op appears immediately after the last instruction of the function.
-These pseudo ops specify the range of the function.
+These pseudo ops specify the range of the function.
Only the order of the other pseudos ops (e.g., @code{.setfp} or
@code{.pad}) matters; their exact locations are irrelevant. In the
Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).
-Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
+Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
memory space and greater than 64K data space (MCU types: atxmega64a1,
atxmega64a1u).
Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
memory space and less than 64K data space (MCU types: atxmega128a3,
-atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3,
+atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3,
atxmega256a3b, atxmega256a3bu, atxmega192d3).
Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
S @r{immediate value from 0 to 7 (S = s << 4)}
? @r{use this opcode entry if no parameters, else use next opcode entry}
-1001010010001000 clc
-1001010011011000 clh
-1001010011111000 cli
-1001010010101000 cln
-1001010011001000 cls
-1001010011101000 clt
-1001010010111000 clv
-1001010010011000 clz
-1001010000001000 sec
-1001010001011000 seh
-1001010001111000 sei
-1001010000101000 sen
-1001010001001000 ses
-1001010001101000 set
-1001010000111000 sev
-1001010000011000 sez
+1001010010001000 clc
+1001010011011000 clh
+1001010011111000 cli
+1001010010101000 cln
+1001010011001000 cls
+1001010011101000 clt
+1001010010111000 clv
+1001010010011000 clz
+1001010000001000 sec
+1001010001011000 seh
+1001010001111000 sei
+1001010000101000 sen
+1001010001001000 ses
+1001010001101000 set
+1001010000111000 sev
+1001010000011000 sez
100101001SSS1000 bclr S
100101000SSS1000 bset S
1001010100001001 icall
-1001010000001001 ijmp
+1001010000001001 ijmp
1001010111001000 lpm ?
1001000ddddd010+ lpm r,z
1001010111011000 elpm ?
1001000ddddd011+ elpm r,z
-0000000000000000 nop
-1001010100001000 ret
-1001010100011000 reti
+0000000000000000 nop
+1001010100001000 ret
+1001010100011000 reti
1001010110001000 sleep
1001010110011000 break
-1001010110101000 wdr
-1001010111101000 spm
+1001010110101000 wdr
+1001010111101000 spm
000111rdddddrrrr adc r,r
000011rdddddrrrr add r,r
001000rdddddrrrr and r,r
100!000dddddee-+ ld r,e
10o0oo1rrrrrbooo std b,r
100!001rrrrree-+ st e,r
-1001010100011001 eicall
-1001010000011001 eijmp
+1001010100011001 eicall
+1001010000011001 eijmp
@end smallexample
@code{-mcpu=} option. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
-recognized:
+recognized:
@code{bf504},
@code{bf506},
@code{bf512},
instruction may appear on the same line. White space (space, tab,
comments or newline) may appear anywhere between tokens. A token must
not have embedded spaces. Tokens include numbers, register names,
-keywords, user identifiers, and also some multicharacter special
+keywords, user identifiers, and also some multicharacter special
symbols like "+=", "/*" or "||".
Comments are introduced by the @samp{#} character and extend to the
@item Instruction Delimiting
A semicolon must terminate every instruction. Sometimes a complete
-instruction will consist of more than one operation. There are two
+instruction will consist of more than one operation. There are two
cases where this occurs. The first is when two general operations
are combined. Normally a comma separates the different parts, as in
Register names are reserved and may not be used as program identifiers.
-Some operations (such as "Move Register") require a register pair.
+Some operations (such as "Move Register") require a register pair.
Register pairs are always data registers and are denoted using a colon,
-eg., R3:2. The larger number must be written firsts. Note that the
+eg., R3:2. The larger number must be written firsts. Note that the
hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
Some instructions (such as --SP (Push Multiple)) require a group of
Again, the larger number appears first.
Portions of a particular register may be individually specified. This
-is written with a dot (".") following the register name and then a
+is written with a dot (".") following the register name and then a
letter denoting the desired portion. For 32-bit registers, ".H"
denotes the most significant ("High") portion. ".L" denotes the
least-significant portion. The subdivisions of the 40-bit registers
@item Data Registers
The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
-normally contain data for manipulation. These are abbreviated as
+normally contain data for manipulation. These are abbreviated as
D-register or Dreg. Data registers can be accessed as 32-bit registers
or as two independent 16-bit registers. The least significant 16 bits
of each register is called the "low" half and is designated with ".L"
@section CR16 Operand Qualifiers
@cindex CR16 Operand Qualifiers
-The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.
+The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.
Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
@table @code
-@item s
+@item s
- @code{Specifies expression operand type as small}
-@item m
+@item m
- @code{Specifies expression operand type as medium}
-@item l
+@item l
- @code{Specifies expression operand type as large}
-@item c
+@item c
- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
-@item got/GOT
+@item got/GOT
- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time}
-@item cgot/cGOT
+@item cgot/cGOT
- @code{Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
@end table
@table @samp
@item Immediate Operand
- s ---- 4 bits
-@item
+@item
- m ---- 16 bits, for movb and movw instructions.
-@item
+@item
- m ---- 20 bits, movd instructions.
-@item
+@item
- l ---- 32 bits
@item Absolute Operand
- s ---- Illegal specifier for this operand.
-@item
+@item
- m ---- 20 bits, movd instructions.
@item Displacement Operand
- s ---- 8 bits
@item
- m ---- 16 bits
-@item
+@item
- l ---- 24 bits
@end table
2 @code{movd $_myfun@@c,(r2,r1)}
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
-
+
3 @code{_myfun_ptr:}
@code{.long _myfun@@c}
@code{loadd _myfun_ptr, (r1,r0)}
5 @code{loadd _myfunc@@cGOT(r12), (r1,r0)}
- This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
+ This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
@end example
@node CR16 Syntax
instructions can be executed in parallel.
@item --nowarnswap
To optimize execution performance, @code{@value{AS}} will sometimes swap the
-order of instructions. Normally this generates a warning. When this option
+order of instructions. Normally this generates a warning. When this option
is used, no warning will be generated when instructions are swapped.
@item --gstabs-packing
@itemx --no-gstabs-packing
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? @code{@value{AS}} will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
-line is being assembled, it will always use the long form. If you need to force the
+line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
-either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
+either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
-in your program, you can write @samp{bra.s foo}.
+in your program, you can write @samp{bra.s foo}.
Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
have both short and long forms.
address will be valid. Nops are automatically inserted when necessary.
If you do not want the assembler automatically making these decisions, you can control
-the packaging and execution type (parallel or sequential) with the special execution
-symbols described in the next section.
+the packaging and execution type (parallel or sequential) with the special execution
+symbols described in the next section.
@node D10V-Chars
@subsection Special Characters
@cindex D10V sub-instruction ordering
Sub-instructions may be executed in order, in reverse-order, or in parallel.
Instructions listed in the standard one-per-line format will be executed sequentially.
-To specify the executing order, use the following symbols:
+To specify the executing order, use the following symbols:
@table @samp
@item ->
Sequential with instruction on the left first.
container, and is executed first.
@item ld2w r2,@@r8+ || mac a0,r0,r7
Execute these in parallel.
-@item ld2w r2,@@r8+ ||
+@item ld2w r2,@@r8+ ||
@itemx mac a0,r0,r7
Two-line format. Execute these in parallel.
-@item ld2w r2,@@r8+
+@item ld2w r2,@@r8+
@itemx mac a0,r0,r7
Two-line format. Execute these sequentially. Assembler will
put them in the proper containers.
@item ld2w r2,@@r8+ ->
@itemx mac a0,r0,r7
Two-line format. Execute these sequentially. Same as above but
-second instruction will always go into right container.
+second instruction will always go into right container.
@end table
@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
@subsection Register Names
@cindex D10V registers
@cindex registers, D10V
-You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
+You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators
-are @samp{a0} and @samp{a1}. There are special register-pair names that may
-optionally be used in opcodes that require even-numbered registers. Register names are
-not case sensitive.
+are @samp{a0} and @samp{a1}. There are special register-pair names that may
+optionally be used in opcodes that require even-numbered registers. Register names are
+not case sensitive.
Register Pairs
@table @code
@item c
Carry flag
@end table
-
+
@node D10V-Addressing
@subsection Addressing Modes
@cindex addressing modes, D10V
@item @@(@var{disp}, R@var{n})
Register indirect with displacement
@item @var{addr}
-PC relative address (for branch or rep).
+PC relative address (for branch or rep).
@item #@var{imm}
Immediate data (the @samp{#} is optional and ignored)
@end table
@cindex D10V floating point
The D10V has no hardware floating point, but the @code{.float} and @code{.double}
directives generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
+with other development tools.
@node D10V-Opcodes
@section Opcodes
@cindex mnemonics, D10V
@cindex instruction summary, D10V
For detailed information on the D10V machine instruction set, see
-@cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
+@cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
(Mitsubishi Electric Corp.).
@code{@value{AS}} implements all the standard D10V opcodes. The only changes are those
described in the section on size modifiers
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? @code{@value{AS}} will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
-line is being assembled, it will always use the long form. If you need to force the
+line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
-either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
+either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
-in your program, you can write @samp{bra.s foo}.
+in your program, you can write @samp{bra.s foo}.
Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
have both short and long forms.
address will be valid. Nops are automatically inserted when necessary.
If you do not want the assembler automatically making these decisions, you can control
-the packaging and execution type (parallel or sequential) with the special execution
-symbols described in the next section.
+the packaging and execution type (parallel or sequential) with the special execution
+symbols described in the next section.
@node D30V-Chars
@subsection Special Characters
Instructions listed in the standard one-per-line format will be executed
sequentially unless you use the @samp{-O} option.
-To specify the executing order, use the following symbols:
+To specify the executing order, use the following symbols:
@table @samp
@item ->
Sequential with instruction on the left first.
@item b
Same as flag 7 (carry/borrow flag)
@end table
-
+
@node D30V-Addressing
@subsection Addressing Modes
@cindex addressing modes, D30V
@item @@(@var{disp}, R@var{n})
Register indirect with displacement
@item @var{addr}
-PC relative address (for branch or rep).
+PC relative address (for branch or rep).
@item #@var{imm}
Immediate data (the @samp{#} is optional and ignored)
@end table
@cindex D30V floating point
The D30V has no hardware floating point, but the @code{.float} and @code{.double}
directives generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
+with other development tools.
@node D30V-Opcodes
@section Opcodes
@cindex mnemonics, D30V
@cindex instruction summary, D30V
For detailed information on the D30V machine instruction set, see
-@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications}
+@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications}
(Mitsubishi Electric Corp.).
@code{@value{AS}} implements all the standard D30V opcodes. The only changes are those
described in the section on size modifiers
@item .h8300hn
Recognize and emit additional instructions for the H8/300H variant in
-normal mode, and also make @code{.int} emit 32-bit numbers rather than
+normal mode, and also make @code{.int} emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
@item .h8300sn
Recognize and emit additional instructions for the H8S variant in
-normal mode, and also make @code{.int} emit 32-bit numbers rather than
+normal mode, and also make @code{.int} emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
@end table
The format of the debugging sections has changed since the original
@code{@value{AS}} port (version 1.3X) was released; therefore,
-you must rebuild all HPPA objects and libraries with the new
+you must rebuild all HPPA objects and libraries with the new
assembler so that you can debug the final executable.
The HPPA @code{@value{AS}} port generates a small subset of the relocations
available in the SOM and ELF object file formats. Additional relocation
-support will be added as it becomes necessary.
+support will be added as it becomes necessary.
@node HPPA Options
@section Options
@example
.endm .liston
.enter .locct
-.leave .macro
+.leave .macro
.listoff
@end example
@itemx .blockz @var{n}
Reserve @var{n} bytes of storage, and initialize them to zero.
-@item .call
+@item .call
Mark the beginning of a procedure call. Only the special case with @emph{no
arguments} is allowed.
@node HPPA Opcodes
@section Opcodes
For detailed information on the HPPA machine instruction set, see
-@cite{PA-RISC Architecture and Instruction Set Reference Manual}
+@cite{PA-RISC Architecture and Instruction Set Reference Manual}
(HP 09740-90039).
@section Notes
The ESA/390 @code{@value{AS}} port is currently intended to be a back-end
for the @sc{gnu} @sc{cc} compiler. It is not HLASM compatible, although
-it does support a subset of some of the HLASM directives. The only
-supported binary file format is ELF; none of the usual MVS/VM/OE/USS
+it does support a subset of some of the HLASM directives. The only
+supported binary file format is ELF; none of the usual MVS/VM/OE/USS
object file formats, such as ESD or XSD, are supported.
When used with the @sc{gnu} @sc{cc} compiler, the ESA/390 @code{@value{AS}}
-will produce correct, fully relocated, functional binaries, and has been
-used to compile and execute large projects. However, many aspects should
-still be considered experimental; these include shared library support,
-dynamically loadable objects, and any relocation other than the 31-bit
+will produce correct, fully relocated, functional binaries, and has been
+used to compile and execute large projects. However, many aspects should
+still be considered experimental; these include shared library support,
+dynamically loadable objects, and any relocation other than the 31-bit
relocation.
@node ESA/390 Options
@node ESA/390 Syntax
@section Syntax
The opcode/operand syntax follows the ESA/390 Principles of Operation
-manual; assembler directives and general syntax are loosely based on the
+manual; assembler directives and general syntax are loosely based on the
prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
-are @emph{not} supported for the most part, with the exception of those
+are @emph{not} supported for the most part, with the exception of those
described herein.
A leading dot in front of directives is optional, and the case of
Since @samp{$} has no special meaning, you may use it in symbol names.
Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6.
-By using thesse symbolic names, @code{@value{AS}} can detect simple
+By using thesse symbolic names, @code{@value{AS}} can detect simple
syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca
-for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
+for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
for r3 and rpgt or r.pgt for r4.
@samp{*} is the current location counter. Unlike @samp{.} it is always
-relative to the last USING directive. Note that this means that
+relative to the last USING directive. Note that this means that
expressions cannot use multiplication, as any occurrence of @samp{*}
will be interpreted as a location counter.
-All labels are relative to the last USING. Thus, branches to a label
+All labels are relative to the last USING. Thus, branches to a label
always imply the use of base+displacement.
-Many of the usual forms of address constants / address literals
+Many of the usual forms of address constants / address literals
are supported. Thus,
@example
.using *,r3
.ltorg
@end example
should all behave as expected: that is, an entry in the literal
-pool will be created (or reused if it already exists), and the
+pool will be created (or reused if it already exists), and the
instruction operands will be the displacement into the literal pool
using the current base register (as last declared with the @code{.using}
directive).
@node ESA/390 Directives
@section ESA/390 Assembler Directives
-@code{@value{AS}} for the ESA/390 supports all of the standard ELF/SVR4
+@code{@value{AS}} for the ESA/390 supports all of the standard ELF/SVR4
assembler directives that are documented in the main part of this
documentation. Several additional directives are supported in order
to implement the ESA/390 addressing model. The most important of these
These are the additional directives in @code{@value{AS}} for the ESA/390:
@table @code
-@item .dc
+@item .dc
A small subset of the usual DC directive is supported.
@item .drop @var{regno}
will be null terminated. Note that the directives @code{.string} etc. emit
ascii strings by default.
-@item EQU
-The standard HLASM-style EQU directive is not supported; however, the
+@item EQU
+The standard HLASM-style EQU directive is not supported; however, the
standard @code{@value{AS}} directive .equ can be used to the same effect.
-@item .ltorg
+@item .ltorg
Dump the literal pool accumulated so far; begin a new literal pool.
The literal pool will be written in the current section; in order to
generate correct assembly, a @code{.using} must have been previously
usually, @var{expr} will merely be @samp{*}.
This assembler allows two @code{.using} directives to be simultaneously
-outstanding, one in the @code{.text} section, and one in another section
-(typically, the @code{.data} section). This feature allows
-dynamically loaded objects to be implemented in a relatively
-straightforward way. A @code{.using} directive must always be specified
+outstanding, one in the @code{.text} section, and one in another section
+(typically, the @code{.data} section). This feature allows
+dynamically loaded objects to be implemented in a relatively
+straightforward way. A @code{.using} directive must always be specified
in the @code{.text} section; this will specify the base register that
will be used for branches in the @code{.text} section. A second
@code{.using} may be specified in another section; this will specify
the base register that is used for non-label address literals.
When a second @code{.using} is specified, then the subsequent
-@code{.ltorg} must be put in the same section; otherwise an error will
+@code{.ltorg} must be put in the same section; otherwise an error will
result.
-Thus, for example, the following code uses @code{r3} to address branch
-targets and @code{r4} to address the literal pool, which has been written
+Thus, for example, the following code uses @code{r3} to address branch
+targets and @code{r4} to address the literal pool, which has been written
to the @code{.data} section. The is, the constants @code{=A(some_routine)},
@code{=H'42'} and @code{=E'3.1416'} will all appear in the @code{.data}
section.
@end example
-Note that this dual-@code{.using} directive semantics extends
-and is not compatible with HLASM semantics. Note that this assembler
+Note that this dual-@code{.using} directive semantics extends
+and is not compatible with HLASM semantics. Note that this assembler
directive does not support the full range of HLASM semantics.
@end table
@cindex options for i386
@cindex options for x86-64
@cindex i386 options
-@cindex x86-64 options
+@cindex x86-64 options
The i386 version of @code{@value{AS}} has a few machine
dependent options:
This option specifies the target processor. The assembler will
issue an error message if an attempt is made to assemble an instruction
which will not execute on the target processor. The following
-processor names are recognized:
+processor names are recognized:
@code{i8086},
@code{i186},
@code{i286},
@code{generic32} and
@code{generic64}.
-In addition to the basic instruction set, the assembler can be told to
+In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics. For example,
@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
@var{vmx}. The following extensions are currently supported:
@cindex @samp{-mmnemonic=} option, x86-64
@item -mmnemonic=@var{att}
@itemx -mmnemonic=@var{intel}
-This option specifies instruction mnemonic for matching instructions.
+This option specifies instruction mnemonic for matching instructions.
The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
take precedent.
@cindex @samp{-msyntax=} option, x86-64
@item -msyntax=@var{att}
@itemx -msyntax=@var{intel}
-This option specifies instruction syntax when processing instructions.
+This option specifies instruction syntax when processing instructions.
The @code{.att_syntax} and @code{.intel_syntax} directives will
take precedent.
BMI instructions provide several instructions implementing individual
bit manipulation operations such as isolation, masking, setting, or
-resetting.
+resetting.
@c Need to add a specification citation here when available.
@end menu
@node Notes-i860
-@section i860 Notes
+@section i860 Notes
This is a fairly complete i860 assembler which is compatible with the
UNIX System V/860 Release 4 assembler. However, it does not currently
support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
(and similarly for the "l" and "h" selectors).
@node Options-i860
@section i860 Command-line Options
-@subsection SVR4 compatibility options
+@subsection SVR4 compatibility options
@table @code
@item -V
Print assembler version.
@item -Qn
Ignored.
@end table
-@subsection Other options
+@subsection Other options
@table @code
@item -EL
Select little endian output (this is the default).
@end smallexample
@item Load/store with relocatable address expression:
-For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
+For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
will be expanded into:
@smallexample
orh addr_exp@@ha,%rx,%r31
If any of the arithmetic operations @code{adds, addu, subs, subu} are used
with an immediate larger than 16-bits (signed), then they will be expanded.
For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
-@smallexample
+@smallexample
orh large_imm@@h,%r0,%r31
or large_imm@@l,%r31,%r31
adds %r31,%rx,%rn
@node Machine Dependencies
@chapter M32C Dependent Features
@end ifclear
-
+
@cindex M32C support
@code{@value{AS}} can assemble code for several different members of
* M32C-Opts:: M32C Options
* M32C-Syntax:: M32C Syntax
@end menu
-
+
@node M32C-Opts
@section M32C Options
-
+
@cindex options, M32C
@cindex M32C options
-
+
The Renesas M32C version of @code{@value{AS}} has these
machine-dependent options:
-
+
@table @code
@item -m32c
@cindex @samp{-m32c} option, M32C
@cindex architecture options, M32C
@cindex M32C architecture option
Assemble M32C instructions.
-
+
@item -m16c
@cindex @samp{-m16c} option, M16C
@cindex architecture options, M16C
@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
-
+
@end table
@node M32C-Syntax
instruction. For example:
@smallexample
- or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
+ or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
@end smallexample
instruction. For example:
@smallexample
- seth r0, #high(0x12345678) ; compute r0 = 0x12340000
+ seth r0, #high(0x12345678) ; compute r0 = 0x12340000
seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
@end smallexample
@cindex @code{shigh} directive, M32R
The @code{shigh} directive is very similar to the @code{high}
directive. It also computes the value of its expression and places
-the upper 16-bits of the result into the immediate-field of the
+the upper 16-bits of the result into the immediate-field of the
instruction. The difference is that @code{shigh} also checks to see
if the lower 16-bits could be interpreted as a signed number, and if
so it assumes that a borrow will occur from the upper-16 bits. To
example:
@smallexample
- seth r0, #shigh(0x00008000)
- add3 r0, r0, #low(0x00008000)
+ seth r0, #shigh(0x00008000)
+ add3 r0, r0, #low(0x00008000)
@end smallexample
Produces the correct result in r0, whereas:
@smallexample
- seth r0, #shigh(0x00008000)
- or3 r0, r0, #low(0x00008000)
+ seth r0, #shigh(0x00008000)
+ or3 r0, r0, #low(0x00008000)
@end smallexample
Stores 0xffff8000 into r0.
This message is produced when the assembler encounters an instruction
which is only supported by the M32Rx processor, and the @samp{-m32rx}
command line flag has not been specified to allow assembly of such
-instructions.
+instructions.
@item unknown instruction @samp{...}
This message is produced when the assembler encounters an instruction
For example these code fragments will produce this message:
@samp{mv r1, r2 || neg r1, r3}
@samp{jl r0 || mv r14, r1}
-@samp{st r2, @@-r1 || mv r1, r3}
-@samp{mv r1, r2 || ld r0, @@r1+}
+@samp{st r2, @@-r1 || mv r1, r3}
+@samp{mv r1, r2 || ld r0, @@r1+}
@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
@end table
The @samp{--force-long-branches} option forces the translation of
relative branches into absolute branches. This option does not affect
the optimization associated to the @samp{jbra}, @samp{jbsr} and
-@samp{jbXX} pseudo opcodes.
+@samp{jbXX} pseudo opcodes.
@cindex @samp{--print-insn-syntax}
@item --print-insn-syntax
bra | bra <pc-rel> <error> | jmp <abs> |
jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
- bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
+ bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
| jmp <abs> | |
+--------------------------+----------------------------------+
@cindex @samp{--base-size-default-16}
@cindex @samp{--base-size-default-32}
-@item --base-size-default-16 --base-size-default-32
+@item --base-size-default-16 --base-size-default-32
If you use an addressing mode with a base register without specifying
the size, @code{@value{AS}} will normally use the full 32 bit value.
For example, the addressing mode @samp{%a0@@(%d0)} is equivalent to
@table @dfn
@item Address Register Indirect
-@samp{(%a0)} through @samp{(%a7)}@*
+@samp{(%a0)} through @samp{(%a7)}@*
@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer. @code{%a6}
is also known as @samp{%fp}, the Frame Pointer.
@cindex comments, M680x0
Line comments are introduced by the @samp{|} character appearing
anywhere on a line, unless the @option{--bitwise-or} command line option
-has been specified.
+has been specified.
An asterisk (@samp{*}) as the first character on a line marks the
start of a line comment as well.
@end ifclear
@cindex MicroBlaze architectures
-The Xilinx MicroBlaze processor family includes several variants, all using
-the same core instruction set. This chapter covers features of the @sc{gnu}
-assembler that are specific to the MicroBlaze architecture. For details about
+The Xilinx MicroBlaze processor family includes several variants, all using
+the same core instruction set. This chapter covers features of the @sc{gnu}
+assembler that are specific to the MicroBlaze architecture. For details about
the MicroBlaze instruction set, please see the @cite{MicroBlaze Processor
Reference Guide (UG081)} available at www.xilinx.com.
@node MicroBlaze Directives
@section Directives
-@cindex MicroBlaze directives
-A number of assembler directives are available for MicroBlaze.
+@cindex MicroBlaze directives
+A number of assembler directives are available for MicroBlaze.
@table @code
@item .data8 @var{expression},...
-This directive is an alias for @code{.byte}. Each expression is assembled
+This directive is an alias for @code{.byte}. Each expression is assembled
into an eight-bit value.
@item .data16 @var{expression},...
-This directive is an alias for @code{.hword}. Each expression is assembled
+This directive is an alias for @code{.hword}. Each expression is assembled
into an 16-bit value.
@item .data32 @var{expression},...
-This directive is an alias for @code{.word}. Each expression is assembled
+This directive is an alias for @code{.word}. Each expression is assembled
into an 32-bit value.
@item .ent @var{name}[,@var{label}]
-This directive is an alias for @code{.func} denoting the start of function
-@var{name} at (optional) @var{label}.
+This directive is an alias for @code{.func} denoting the start of function
+@var{name} at (optional) @var{label}.
@item .end @var{name}[,@var{label}]
-This directive is an alias for @code{.endfunc} denoting the end of function
+This directive is an alias for @code{.endfunc} denoting the end of function
@var{name}.
@item .gpword @var{label},...
.word 0x0
baz:
.word 0x1
-
+
@end example
@node MIPS option stack
@item -m
select the mpu arch. Currently has no effect.
-@item -mP
+@item -mP
enables polymorph instructions handler.
-@item -mQ
+@item -mQ
enables relaxation at assembly time. DANGEROUS!
@end table
@table @code
-@item llo(exp)
+@item llo(exp)
Extracts least significant word from 32-bit expression 'exp'.
@item lhi(exp)
@item hlo(exp)
Extracts 3rd word from 64-bit expression 'exp'.
-@item hhi(exp)
+@item hhi(exp)
Extracts 4rd word from 64-bit expression 'exp'.
@end table
They normally being used as an immediate source operand.
@smallexample
- mov #llo(1), r10 ; == mov #1, r10
+ mov #llo(1), r10 ; == mov #1, r10
mov #lhi(1), r10 ; == mov #0, r10
@end smallexample
-
+
@node MSP430-Chars
@subsection Special Characters
@cindex identifiers, MSP 430
@cindex MSP 430 identifiers
-The character @samp{$} in jump instructions indicates current location and
+The character @samp{$} in jump instructions indicates current location and
implemented only for TI syntax compatibility.
@node MSP430-Regs
@samp{flags} is a combination of the following characters:
-@item s
+@item s
function entry
-@item x
+@item x
function exit
-@item i
+@item i
function is in init section
-@item f
+@item f
function is in fini section
-@item l
+@item l
library call
-@item c
+@item c
libc standard call
-@item d
+@item d
stack value demand
-@item I
+@item I
interrupt service routine
-@item P
+@item P
prologue start
-@item p
+@item p
prologue end
-@item E
+@item E
epilogue start
-@item e
+@item e
epilogue end
-@item j
+@item j
long jump / sjlj unwind
-@item a
+@item a
an arbitrary code fragment
@item t
extra parameter saved (a constant value like frame size)
@end table
-@item function_to_profile
+@item function_to_profile
a function address
-@item cycle_corrector
+@item cycle_corrector
a value which should be added to the cycle counter, zero if omitted.
-@item extra
+@item extra
any extra parameter, zero if omitted.
@end table
push r8
.profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
; (this is a prologue end)
- ; note, that spare var filled with
+ ; note, that spare var filled with
; the farme size
mov r15,r8
...
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
-recognized:
+recognized:
@code{ms1-64-001},
@code{ms1-16-002},
@code{ms1-16-003},
@cindex s390 options
The following table lists all available s390 specific options:
-
+
@table @code
@cindex @samp{-m31} option, s390
@cindex @samp{-m64} option, s390
@cindex @samp{-march=} option, s390
@item -march=@var{CPU}
This option specifies the target processor. The following processor names
-are recognized:
+are recognized:
@code{g5},
@code{g6},
@code{z900},
@cindex instruction syntax, s390
@cindex s390 instruction syntax
-The assembler syntax closely follows the syntax outlined in
-Enterprise Systems Architecture/390 Principles of Operation (SA22-7201)
-and the z/Architecture Principles of Operation (SA22-7832).
+The assembler syntax closely follows the syntax outlined in
+Enterprise Systems Architecture/390 Principles of Operation (SA22-7201)
+and the z/Architecture Principles of Operation (SA22-7832).
Each instruction has two major parts, the instruction mnemonic
and the instruction operands. The instruction format varies.
The Principles of Operation manuals lists 26 instruction formats where
some of the formats have multiple variants. For the @samp{.insn}
-pseudo directive the assembler recognizes some of the formats.
+pseudo directive the assembler recognizes some of the formats.
Typically, the most general variant of the instruction format is used
by the @samp{.insn} directive.
+--------+----+----+
| OpCode | R1 | R2 |
+--------+----+----+
-0 8 12 15
+0 8 12 15
@end verbatim
@item RRE format: <insn> R1,R2
symbol.
@item @@gotoff
The @@gotoff modifier can be used for 16-bit immediate fields. The symbol
-term is replaced with the offset from the start of the GOT to the
+term is replaced with the offset from the start of the GOT to the
address of the symbol.
@item @@gotplt
The @@gotplt modifier can be used for displacement fields, 16-bit immediate
The @@gotntpoff modifier can be used for displacement fields. The symbol
is added to the static TLS block and the negated offset to the symbol
in the static TLS block is added to the GOT. The symbol term is replaced
-with the offset to the GOT slot from the start of the GOT.
+with the offset to the GOT slot from the start of the GOT.
@item @@indntpoff
The @@indntpoff modifier can be used for 32-bit pc-relative immediate
fields. The symbol is added to the static TLS block and the negated offset
@item :tls_load
The :tls_load marker is used to flag the load instruction in the initial
exec TLS model that retrieves the offset from the thread pointer to a
-thread local storage variable from the GOT.
+thread local storage variable from the GOT.
@item :tls_gdcall
The :tls_gdcall marker is used to flag the branch-and-save instruction to
the __tls_get_offset function in the global dynamic TLS model.
@node s390 Directives
@section Assembler Directives
-@code{@value{AS}} for s390 supports all of the standard ELF
+@code{@value{AS}} for s390 supports all of the standard ELF
assembler directives as outlined in the main part of this document.
Some directives have been extended and there are some additional
directives, which are only available for the s390 @code{@value{AS}}.
@itemx .quad
This directive places one or more 16-bit (.short), 32-bit (.long), or
64-bit (.quad) values into the current section. If an ELF or TLS modifier
-is used only the following expressions are allowed:
+is used only the following expressions are allowed:
@samp{symbol@@modifier + constant},
@samp{symbol@@modifier + label + constant}, and
@samp{symbol@@modifier - label + constant}.
* SCORE-Syntax:: Syntax
@end menu
-@node SCORE-Opts
+@node SCORE-Opts
@section Options
@cindex options for SCORE
@item -EL
Assemble code for a little-endian cpu
-@item -FIXDD
+@item -FIXDD
Assemble code for fix data dependency
-@item -NWARN
+@item -NWARN
Assemble code for no warning message for fix data dependency
@item -SCORE5
@item -march=score3
Assemble code for target is SCORE3
-@item -USE_R1
+@item -USE_R1
Assemble code for no warning message when using temp register r1
@item -KPIC
@item -O0
Assembler will not perform any optimizations
-@item -V
+@item -V
Sunplus release version
@end table
following table is far from complete.
@table @code
-@item .set nwarn
-Let the assembler not to generate warnings if the source machine
+@item .set nwarn
+Let the assembler not to generate warnings if the source machine
language instructions happen data dependency.
-@item .set fixdd
-Let the assembler to insert bubbles (32 bit nop instruction /
-16 bit nop! Instruction) if the source machine language instructions
+@item .set fixdd
+Let the assembler to insert bubbles (32 bit nop instruction /
+16 bit nop! Instruction) if the source machine language instructions
happen data dependency.
-@item .set nofixdd
-Let the assembler to generate warnings if the source machine
+@item .set nofixdd
+Let the assembler to generate warnings if the source machine
language instructions happen data dependency. (Default)
@item .set r1
-Let the assembler not to generate warnings if the source program
-uses r1. allow user to use r1
+Let the assembler not to generate warnings if the source program
+uses r1. allow user to use r1
@item set nor1
Let the assembler to generate warnings if the source program uses
r1. (Default)
@item .sdata
-Tell the assembler to add subsequent data into the sdata section
+Tell the assembler to add subsequent data into the sdata section
@item .rdata
Tell the assembler to add subsequent data into the rdata section
@item .frame "frame-register", "offset", "return-pc-register"
-Describe a stack frame. "frame-register" is the frame register,
-"offset" is the distance from the frame register to the virtual
-frame pointer, "return-pc-register" is the return program register.
-You must use ".ent" before ".frame" and only one ".frame" can be
-used per ".ent".
+Describe a stack frame. "frame-register" is the frame register,
+"offset" is the distance from the frame register to the virtual
+frame pointer, "return-pc-register" is the return program register.
+You must use ".ent" before ".frame" and only one ".frame" can be
+used per ".ent".
@item .mask "bitmask", "frameoffset"
-Indicate which of the integer registers are saved in the current
-function's stack frame, this is for the debugger to explain the
+Indicate which of the integer registers are saved in the current
+function's stack frame, this is for the debugger to explain the
frame chain.
@item .ent "proc-name"
-Set the beginning of the procedure "proc_name". Use this directive
-when you want to generate information for the debugger.
+Set the beginning of the procedure "proc_name". Use this directive
+when you want to generate information for the debugger.
@item .end proc-name
-Set the end of a procedure. Use this directive to generate information
-for the debugger.
+Set the end of a procedure. Use this directive to generate information
+for the debugger.
@item .bss
-Switch the destination of following statements into the bss section,
-which is used for data that is uninitialized anywhere.
+Switch the destination of following statements into the bss section,
+which is used for data that is uninitialized anywhere.
@end table
@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
-SH groups can use @code{.float} directive to generate @sc{ieee}
-floating-point numbers.
+SH groups can use @code{.float} directive to generate @sc{ieee}
+floating-point numbers.
-SH2E and SH3E support single-precision floating point calculations as
-well as entirely PCAPI compatible emulation of double-precision
+SH2E and SH3E support single-precision floating point calculations as
+well as entirely PCAPI compatible emulation of double-precision
floating point calculations. SH2E and SH3E instructions are a subset of
the floating point calculations conforming to the IEEE754 standard.
-In addition to single-precision and double-precision floating-point
-operation capability, the on-chip FPU of SH4 has a 128-bit graphic
-engine that enables 32-bit floating-point data to be processed 128
-bits at a time. It also supports 4 * 4 array operations and inner
-product operations. Also, a superscalar architecture is employed that
-enables simultaneous execution of two instructions (including FPU
-instructions), providing performance of up to twice that of
+In addition to single-precision and double-precision floating-point
+operation capability, the on-chip FPU of SH4 has a 128-bit graphic
+engine that enables 32-bit floating-point data to be processed 128
+bits at a time. It also supports 4 * 4 array operations and inner
+product operations. Also, a superscalar architecture is employed that
+enables simultaneous execution of two instructions (including FPU
+instructions), providing performance of up to twice that of
conventional architectures at the same frequency.
@node SH Directives
disp8 @r{8-bit displacement}
disp12 @r{12-bit displacement}
-add #imm,Rn lds.l @@Rn+,PR
-add Rm,Rn mac.w @@Rm+,@@Rn+
-addc Rm,Rn mov #imm,Rn
-addv Rm,Rn mov Rm,Rn
-and #imm,R0 mov.b Rm,@@(R0,Rn)
-and Rm,Rn mov.b Rm,@@-Rn
-and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
-bf disp8 mov.b @@(disp,Rm),R0
-bra disp12 mov.b @@(disp,GBR),R0
-bsr disp12 mov.b @@(R0,Rm),Rn
-bt disp8 mov.b @@Rm+,Rn
-clrmac mov.b @@Rm,Rn
-clrt mov.b R0,@@(disp,Rm)
-cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
-cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
-cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
-cmp/gt Rm,Rn mov.l Rm,@@-Rn
-cmp/hi Rm,Rn mov.l Rm,@@Rn
-cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
-cmp/pl Rn mov.l @@(disp,GBR),R0
-cmp/pz Rn mov.l @@(disp,PC),Rn
-cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
-div0s Rm,Rn mov.l @@Rm+,Rn
-div0u mov.l @@Rm,Rn
-div1 Rm,Rn mov.l R0,@@(disp,GBR)
-exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
-exts.w Rm,Rn mov.w Rm,@@-Rn
-extu.b Rm,Rn mov.w Rm,@@Rn
-extu.w Rm,Rn mov.w @@(disp,Rm),R0
-jmp @@Rn mov.w @@(disp,GBR),R0
-jsr @@Rn mov.w @@(disp,PC),Rn
-ldc Rn,GBR mov.w @@(R0,Rm),Rn
-ldc Rn,SR mov.w @@Rm+,Rn
-ldc Rn,VBR mov.w @@Rm,Rn
-ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
-ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
-ldc.l @@Rn+,VBR mova @@(disp,PC),R0
-lds Rn,MACH movt Rn
-lds Rn,MACL muls Rm,Rn
-lds Rn,PR mulu Rm,Rn
-lds.l @@Rn+,MACH neg Rm,Rn
-lds.l @@Rn+,MACL negc Rm,Rn
+add #imm,Rn lds.l @@Rn+,PR
+add Rm,Rn mac.w @@Rm+,@@Rn+
+addc Rm,Rn mov #imm,Rn
+addv Rm,Rn mov Rm,Rn
+and #imm,R0 mov.b Rm,@@(R0,Rn)
+and Rm,Rn mov.b Rm,@@-Rn
+and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
+bf disp8 mov.b @@(disp,Rm),R0
+bra disp12 mov.b @@(disp,GBR),R0
+bsr disp12 mov.b @@(R0,Rm),Rn
+bt disp8 mov.b @@Rm+,Rn
+clrmac mov.b @@Rm,Rn
+clrt mov.b R0,@@(disp,Rm)
+cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
+cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
+cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
+cmp/gt Rm,Rn mov.l Rm,@@-Rn
+cmp/hi Rm,Rn mov.l Rm,@@Rn
+cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
+cmp/pl Rn mov.l @@(disp,GBR),R0
+cmp/pz Rn mov.l @@(disp,PC),Rn
+cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
+div0s Rm,Rn mov.l @@Rm+,Rn
+div0u mov.l @@Rm,Rn
+div1 Rm,Rn mov.l R0,@@(disp,GBR)
+exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
+exts.w Rm,Rn mov.w Rm,@@-Rn
+extu.b Rm,Rn mov.w Rm,@@Rn
+extu.w Rm,Rn mov.w @@(disp,Rm),R0
+jmp @@Rn mov.w @@(disp,GBR),R0
+jsr @@Rn mov.w @@(disp,PC),Rn
+ldc Rn,GBR mov.w @@(R0,Rm),Rn
+ldc Rn,SR mov.w @@Rm+,Rn
+ldc Rn,VBR mov.w @@Rm,Rn
+ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
+ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
+ldc.l @@Rn+,VBR mova @@(disp,PC),R0
+lds Rn,MACH movt Rn
+lds Rn,MACL muls Rm,Rn
+lds Rn,PR mulu Rm,Rn
+lds.l @@Rn+,MACH neg Rm,Rn
+lds.l @@Rn+,MACL negc Rm,Rn
@page
-nop stc VBR,Rn
-not Rm,Rn stc.l GBR,@@-Rn
-or #imm,R0 stc.l SR,@@-Rn
-or Rm,Rn stc.l VBR,@@-Rn
-or.b #imm,@@(R0,GBR) sts MACH,Rn
-rotcl Rn sts MACL,Rn
-rotcr Rn sts PR,Rn
-rotl Rn sts.l MACH,@@-Rn
-rotr Rn sts.l MACL,@@-Rn
-rte sts.l PR,@@-Rn
-rts sub Rm,Rn
-sett subc Rm,Rn
-shal Rn subv Rm,Rn
-shar Rn swap.b Rm,Rn
-shll Rn swap.w Rm,Rn
-shll16 Rn tas.b @@Rn
-shll2 Rn trapa #imm
-shll8 Rn tst #imm,R0
-shlr Rn tst Rm,Rn
-shlr16 Rn tst.b #imm,@@(R0,GBR)
-shlr2 Rn xor #imm,R0
-shlr8 Rn xor Rm,Rn
-sleep xor.b #imm,@@(R0,GBR)
-stc GBR,Rn xtrct Rm,Rn
+nop stc VBR,Rn
+not Rm,Rn stc.l GBR,@@-Rn
+or #imm,R0 stc.l SR,@@-Rn
+or Rm,Rn stc.l VBR,@@-Rn
+or.b #imm,@@(R0,GBR) sts MACH,Rn
+rotcl Rn sts MACL,Rn
+rotcr Rn sts PR,Rn
+rotl Rn sts.l MACH,@@-Rn
+rotr Rn sts.l MACL,@@-Rn
+rte sts.l PR,@@-Rn
+rts sub Rm,Rn
+sett subc Rm,Rn
+shal Rn subv Rm,Rn
+shar Rn swap.b Rm,Rn
+shll Rn swap.w Rm,Rn
+shll16 Rn tas.b @@Rn
+shll2 Rn trapa #imm
+shll8 Rn tst #imm,R0
+shlr Rn tst Rm,Rn
+shlr16 Rn tst.b #imm,@@(R0,GBR)
+shlr2 Rn xor #imm,R0
+shlr8 Rn xor Rm,Rn
+sleep xor.b #imm,@@(R0,GBR)
+stc GBR,Rn xtrct Rm,Rn
stc SR,Rn
@end smallexample
@end ifset
@item .abi [32|64]
Specify the ABI for the following instructions. Note that you cannot use
-this directive unless you specified an ABI on the command line, and the
+this directive unless you specified an ABI on the command line, and the
ABIs specified must match.
@end table
All addresses will be assumed to be > 16 bits, and the appropriate
relocation types will be used. This option is equivalent to using the
@samp{.far_mode} directive in the assembly code. If you do not use the
-@samp{-mfar-mode} option, all references will be assumed to be 16 bits.
+@samp{-mfar-mode} option, all references will be assumed to be 16 bits.
This option may be abbreviated to @samp{-mf}.
@cindex @samp{-mcpu} option, cpu
This option is equivalent to using the @samp{.version} directive in the
assembly code. For recognized CPU codes, see
@xref{TIC54X-Directives,,@code{.version}}. The default CPU version is
-@samp{542}.
+@samp{542}.
@cindex @samp{-merrors-to-file} option, stderr redirect
@cindex @samp{-me} option, stderr redirect
You can use the @samp{-merrors-to-file} option to redirect error output
to a file (this provided for those deficient environments which don't
provide adequate output redirection). This option may be abbreviated to
-@samp{-me}.
+@samp{-me}.
@node TIC54X-Block
@section Blocking
arbitrary string values. This is roughly equivalent to C preprocessor
#define macros. When @code{@value{AS}} encounters one of these
symbols, the symbol is replaced in the input stream by its string value.
-Subsym names @strong{must} begin with a letter.
+Subsym names @strong{must} begin with a letter.
Subsyms may be defined using the @code{.asg} and @code{.eval} directives
(@xref{TIC54X-Directives,,@code{.asg}},
-@xref{TIC54X-Directives,,@code{.eval}}.
+@xref{TIC54X-Directives,,@code{.eval}}.
Expansion is recursive until a previously encountered symbol is seen, at
-which point substitution stops.
+which point substitution stops.
In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1
is replaced with x. At this point, x has already been encountered
and the substitution stops.
@smallexample @code
- .asg "x",SYM1
+ .asg "x",SYM1
.asg "SYM1",SYM2
.asg "SYM2",x
add x,a ; final code assembled is "add x, a"
Substitution may be forced in situations where replacement might be
ambiguous by placing colons on either side of the subsym. The following
-code:
+code:
@smallexample @code
.eval "10",x
@item
$N, where N is a decimal number between 0 and 9
@item
-LABEL?, where LABEL is any legal symbol name.
+LABEL?, where LABEL is any legal symbol name.
@end itemize
Local labels thus defined may be redefined or automatically generated.
The following built-in functions may be used to generate a
floating-point value. All return a floating-point value except
@samp{$cvi}, @samp{$int}, and @samp{$sgn}, which return an integer
-value.
+value.
@table @code
@cindex @code{$acos} math builtin, TIC54X
Align SPC to word boundary
@item 2
Align SPC to longword boundary (same as .even)
-@item 128
+@item 128
Align SPC to page boundary
@end table
@item .eval @var{string}, @var{name}
Evaluate the contents of string @var{string} and assign the result as a
string to the subsym @var{name}. String replacement is performed on
-@var{string} before assignment.
+@var{string} before assignment.
@cindex @code{bss} directive, TIC54X
@item .bss @var{symbol}, @var{size} [, [@var{blocking_flag}] [,@var{alignment_flag}]]
Place an IEEE single-precision floating-point representation of one or
more floating-point values into the current section. All but
@code{.xfloat} align the result on a longword boundary. Values are
-stored most-significant word first.
+stored most-significant word first.
@cindex @code{drlist} directive, TIC54X
@cindex @code{drnolist} directive, TIC54X
@itemx .uword @var{value} [,...,@var{value_n}]
Place one or more values into consecutive words of the current section.
If a label is used, it points to the word allocated for the first value
-encountered.
+encountered.
@cindex @code{label} directive, TIC54X
@item .label @var{symbol}
Place one or more 32-bit values into consecutive words in the current
section. The most significant word is stored first. @code{.long} and
@code{.ulong} align the result on a longword boundary; @code{xlong} does
-not.
+not.
@cindex @code{loop} directive, TIC54X
@cindex @code{break} directive, TIC54X
@item @var{symbol} .set "@var{value}"
@itemx @var{symbol} .equ "@var{value}"
Equate a constant @var{value} to a @var{symbol}, which is placed in the
-symbol table. @var{symbol} may not be previously defined.
+symbol table. @var{symbol} may not be previously defined.
@cindex @code{space} directive, TIC54X
@cindex @code{bes} directive, TIC54X
structure/union element within a structure, may be used to apply a
structure to a symbol. Once applied to @var{label}, the individual
structure elements may be applied to @var{label} to produce the desired
-offsets using @var{label} as the structure base.
+offsets using @var{label} as the structure base.
@cindex @code{tab} directive, TIC54X
@item .tab
@cindex @code{union} directive, TIC54X
@cindex @code{tag} directive, TIC54X
@cindex @code{endunion} directive, TIC54X
-@item [@var{utag}] .union
+@item [@var{utag}] .union
@itemx [@var{name_1}] element [@var{count_1}]
@itemx [@var{name_2}] element [@var{count_2}]
@itemx [@var{tname}] .tag @var{utagx}[,@var{tcount}]
size in words. @var{blocking_flag} indicates whether to block this
section on a page boundary (128 words) (@pxref{TIC54X-Block}).
@var{alignment flag} indicates whether the section should be
-longword-aligned.
+longword-aligned.
@cindex @code{var} directive, TIC54X
@item .var @var{sym}[,..., @var{sym_n}]
Define a subsym to be a local variable within a macro. See
-@xref{TIC54X-Macros}.
+@xref{TIC54X-Macros}.
@cindex @code{version} directive, TIC54X
@item .version @var{version}
@cindex TIC54X-specific macros
@cindex macros, TIC54X
-Macros do not require explicit dereferencing of arguments (i.e., \ARG).
+Macros do not require explicit dereferencing of arguments (i.e., \ARG).
During macro expansion, the macro parameters are converted to subsyms.
If the number of arguments passed the macro invocation exceeds the
@cindex @code{$symcmp} subsym builtin, TIC54X
@item @code{$symcmp(@var{str1},@var{str2})}
-Returns 0 if @var{str1} == @var{str2}, non-zero otherwise.
+Returns 0 if @var{str1} == @var{str2}, non-zero otherwise.
@cindex @code{$firstch} subsym builtin, TIC54X
@item @code{$firstch(@var{str},@var{ch})}
Returns index of the first occurrence of character constant @var{ch} in
-@var{str}.
+@var{str}.
@cindex @code{$lastch} subsym builtin, TIC54X
@item @code{$lastch(@var{str},@var{ch})}
Returns index of the last occurrence of character constant @var{ch} in
-@var{str}.
+@var{str}.
@cindex @code{$isdefed} subsym builtin, TIC54X
@item @code{$isdefed(@var{symbol})}
@cindex @code{.personalityindex} directive, TIC6X
@item .personalityindex @var{index}
-Sets the personality routine for the current function to the ABI specified
+Sets the personality routine for the current function to the ABI specified
compact routine number @var{index}
@cindex @code{.personality} directive, TIC6X
@table @code
@cindex @code{offset} directive, V850
@item .offset @var{<expression>}
-Moves the offset into the current section to the specified amount.
+Moves the offset into the current section to the specified amount.
@cindex @code{section} directive, V850
@item .section "name", <type>
This is an extension to the standard .section directive. It sets the
current section to be <type> and creates an alias for this section
-called "name".
+called "name".
@cindex @code{.v850} directive, V850
@item .v850
computes the difference between the address of labels 'here' and
'there', takes the upper 16 bits of this difference, shifts it down 16
bits and then multiplies it by the lower 16 bits in register 5, putting
-the result into register 6.
+the result into register 6.
@cindex @code{lo} pseudo-op, V850
@item lo()
@samp{mov hilo(here), r6}
computes the absolute address of label 'here' and puts the result into
-register 6.
+register 6.
@cindex @code{sdaoff} pseudo-op, V850
@item sdaoff()
Computes the offset of the named variable from the start of the Small
Data Area (whoes address is held in register 4, the GP register) and
stores the result as a 16 bit signed value in the immediate operand
-field of the given instruction. For example:
+field of the given instruction. For example:
@samp{ld.w sdaoff(_a_variable)[gp],r6}
@cindex @code{ascii} directive, xc16x
@item .ascii "@var{ascii}"
-This directive used for copying @var{str} into the object file.
+This directive used for copying @var{str} into the object file.
The string is terminated with a null byte.
@cindex @code{set} directive, xc16x
aligned to the power of two specified by @var{align}. @var{length} and
@var{align} must be positive absolute expressions. This directive
differs from @samp{.lcomm} only in that it permits you to specify
-an alignment.
+an alignment.
@end table
@node xc16x Syntax
@end table
-Convience macro opcodes to deal with 16-bit values have been added.
+Convience macro opcodes to deal with 16-bit values have been added.
@table @dfn
@subsection literal
@cindex @code{literal} directive
-The @code{.literal} directive is used to define literal pool data, i.e.,
+The @code{.literal} directive is used to define literal pool data, i.e.,
read-only 32-bit data accessed via @code{L32R} instructions.
@smallexample
@samp{--text-@-section-@-literals} option is not used or when
@code{L32R} instructions use the absolute addressing mode.
-The assembler will automatically place text section literal pools
+The assembler will automatically place text section literal pools
before @code{ENTRY} instructions, so the @code{.literal_position}
directive is only needed to specify some other location for a literal
pool. You may need to add an explicit jump instruction to skip over an
The assembler syntax closely follows the 'Z80 family CPU User Manual' by
Zilog.
In expressions a single @samp{=} may be used as ``is equal to''
-comparison operator.
+comparison operator.
Suffices can be used to indicate the radix of integer constants;
@samp{H} or @samp{h} for hexadecimal, @samp{D} or @samp{d} for decimal,
@samp{Q}, @samp{O}, @samp{q} or @samp{o} for octal, and @samp{B} for
binary.
-The suffix @samp{b} denotes a backreference to local label.
+The suffix @samp{b} denotes a backreference to local label.
@menu
* Z80-Chars:: Special Characters
@cindex line comment character, Z80
@cindex Z80 line comment character
-The semicolon @samp{;} is the line comment character;
+The semicolon @samp{;} is the line comment character;
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
@cindex character escapes, Z80
@cindex Z80, \
A backslash @samp{\} is an ordinary character for the Z80 assembler.
-
+
@cindex character constant, Z80
@cindex single quote, Z80
@cindex Z80 '
@cindex register names, Z80
The registers are referred to with the letters assigned to them by
-Zilog. In addition @command{@value{AS}} recognizes @samp{ixl} and
+Zilog. In addition @command{@value{AS}} recognizes @samp{ixl} and
@samp{ixh} as the least and most significant octet in @samp{ix}, and
-similarly @samp{iyl} and @samp{iyh} as parts of @samp{iy}.
+similarly @samp{iyl} and @samp{iyh} as parts of @samp{iy}.
@c The @samp{'} in @samp{ex af,af'} may be omitted.
@cindex case sensitivity, Z80
Upper and lower case are equivalent in register names, opcodes,
-condition codes and assembler directives.
+condition codes and assembler directives.
The case of letters is significant in labels and symbol names. The case
is also important to distinguish the suffix @samp{b} for a backward reference
to a local label from the suffix @samp{B} for a number in binary notation.
@section Z80 Assembler Directives
@command{@value{AS}} for the Z80 supports some additional directives for
-compatibility with other assemblers.
+compatibility with other assemblers.
@cindex Z80-only directives
These are the additional directives in @code{@value{AS}} for the Z80:
@item db @var{expression}|@var{string}[,@var{expression}|@var{string}...]
@itemx defb @var{expression}|@var{string}[,@var{expression}|@var{string}...]
For each @var{string} the characters are copied to the object file, for
-each other @var{expression} the value is stored in one byte.
-A warning is issued in case of an overflow.
+each other @var{expression} the value is stored in one byte.
+A warning is issued in case of an overflow.
@item dw @var{expression}[,@var{expression}...]
@itemx defw @var{expression}[,@var{expression}...]
For each @var{expression} the value is stored in two bytes, ignoring
-overflow.
+overflow.
@item d24 @var{expression}[,@var{expression}...]
@itemx def24 @var{expression}[,@var{expression}...]
For each @var{expression} the value is stored in three bytes, ignoring
-overflow.
+overflow.
@item d32 @var{expression}[,@var{expression}...]
@itemx def32 @var{expression}[,@var{expression}...]
For each @var{expression} the value is stored in four bytes, ignoring
-overflow.
+overflow.
@item ds @var{count}[, @var{value}]
@itemx defs @var{count}[, @var{value}]
-@c Synonyms for @code{ds.b},
+@c Synonyms for @code{ds.b},
@c which should have been described elsewhere
Fill @var{count} bytes in the object file with @var{value}, if
@var{value} is omitted it defaults to zero.
Symbols defined with @code{equ} are not protected from redefinition.
@item set
-This is a normal instruction on Z80, and not an assembler directive.
+This is a normal instruction on Z80, and not an assembler directive.
@item psect @var{name}
-A synonym for @xref{Section}, no second argument should be given.
+A synonym for @xref{Section}, no second argument should be given.
@ignore
The following attributes will possibly be recognized in the future
@node Z80 Opcodes
@section Opcodes
In line with common practice, Z80 mnemonics are used for both the Z80 and
-the R800.
+the R800.
In many instructions it is possible to use one of the half index
registers (@samp{ixl},@samp{ixh},@samp{iyl},@samp{iyh}) in stead of an
synonym for @samp{sli}.
@item @var{op} (ix+@var{d}), @var{r}
-This is equivalent to
+This is equivalent to
@example
ld @var{r}, (ix+@var{d})
@cindex TC_FINALIZE_SYMS_BEFORE_SIZE_SEG
Specifies the value to be assigned to @code{finalize_syms} before the function
@code{size_segs} is called. Since @code{size_segs} calls @code{cvt_frag_to_fill}
-which can call @code{md_convert_frag}, this constant governs whether the symbols
+which can call @code{md_convert_frag}, this constant governs whether the symbols
accessed in @code{md_convert_frag} will be fully resolved. In particular it
governs whether local symbols will have been resolved, and had their frag
information removed. Depending upon the processing performed by
#if SUPPORT_FRAME_LINKONCE
#define CUR_SEG(structp) structp->cur_seg
-#define SET_CUR_SEG(structp, seg) structp->cur_seg = seg
+#define SET_CUR_SEG(structp, seg) structp->cur_seg = seg
#define HANDLED(structp) structp->handled
#define SET_HANDLED(structp, val) structp->handled = val
#else
returned. */
extern void dwarf2_where (struct dwarf2_line_info *l);
-/* A hook to allow the target backend to inform the line number state
+/* A hook to allow the target backend to inform the line number state
machine of isa changes when assembler debug info is enabled. */
extern void dwarf2_set_isa (unsigned int isa);
extern bfd_boolean dwarf2_loc_directive_seen;
/* True when we're supposed to set the basic block mark whenever a label
- is seen. Unless the target is doing Something Weird, just call
+ is seen. Unless the target is doing Something Weird, just call
dwarf2_emit_label. */
extern bfd_boolean dwarf2_loc_mark_labels;
free (coff_sym_name);
if (coff_tag != (char *) NULL)
free (coff_tag);
-
+
coff_sym_name = xstrdup (name);
coff_type = type_info_init;
coff_storage_class = sc_Nil;
if (feof (f_in))
return 0;
-
+
size = fread (buf, sizeof (char), buflen, f_in);
if (ferror (f_in))
as_bad (_("can't read from %s: %s"), file_name, xstrerror (errno));
the Free Software Foundation; either version 3, or (at your option)
any later version.
- GAS is distributed in the hope that it will be useful,
+ GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
if (stdoutput == NULL)
return;
-
+
/* Close the bfd. */
if (had_errors ())
res = bfd_cache_close_all ();
name_end = start + len;
name = start + sofar;
}
-
+
*name++ = (char) C;
}
*name = 0;
ignore_rest_of_line ();
return NULL;
}
-
+
SKIP_WHITESPACE ();
return start;
{
sb_to_scrub = s;
scrub_position = s->ptr;
-
+
sb_check (ptr, s->len);
ptr->len += do_scrub_chars (scrub_from_sb, ptr->ptr + ptr->len, s->len);
if (!seginfo)
return 0;
-
+
for (chain = seginfo->frchainP; chain; chain = chain->frch_next)
{
for (frag = chain->frch_root; frag; frag = frag->fr_next)
if ( (S_IS_COMMON (symp->sy_value.X_add_symbol)
|| S_IS_LOCAL (symp->sy_value.X_add_symbol))
- &&
+ &&
(S_IS_COMMON (symp->sy_value.X_op_symbol)
|| S_IS_LOCAL (symp->sy_value.X_op_symbol))
&& S_GET_SEGMENT (symp->sy_value.X_op_symbol) != expr_section)
return 0;
break;
-
+
default:
break;
}
if (symp->bsym->flags & BSF_SRELC)
relc_symbol->bsym->flags |= BSF_SRELC;
else
- relc_symbol->bsym->flags |= BSF_RELC;
+ relc_symbol->bsym->flags |= BSF_RELC;
/* symp->bsym->flags |= BSF_RELC; */
copy_symbol_attributes (symp, relc_symbol);
symp->sy_value.X_op = O_symbol;
gas_assert (exp != NULL);
/* Match known operators -> fill in opstr, arity, operands[] and fall
- through to construct subexpression fragments; may instead return
+ through to construct subexpression fragments; may instead return
string directly for leaf nodes. */
- /* See expr.h for the meaning of all these enums. Many operators
+ /* See expr.h for the meaning of all these enums. Many operators
have an unnatural arity (X_add_number implicitly added). The
conversion logic expands them to explicit "+" subexpressions. */
return symbol_relc_make_value (exp->X_add_number);
case O_symbol:
- if (exp->X_add_number)
- {
- arity = 2;
- opstr = "+";
+ if (exp->X_add_number)
+ {
+ arity = 2;
+ opstr = "+";
operands[0] = symbol_relc_make_sym (exp->X_add_symbol);
operands[1] = symbol_relc_make_value (exp->X_add_number);
break;
operands[0] = symbol_relc_make_sym (exp->X_add_symbol); \
} \
break
-
+
#define HANDLE_XADD_OPT2(str_) \
if (exp->X_add_number) \
{ \
else
{
/* Allocate new string; include inter-operand padding gaps etc. */
- concat_string = xmalloc (strlen (opstr)
+ concat_string = xmalloc (strlen (opstr)
+ 1
+ (arity >= 1 ? (strlen (operands[0]) + 1 ) : 0)
+ (arity >= 2 ? (strlen (operands[1]) + 1 ) : 0)
+ (arity >= 3 ? (strlen (operands[2]) + 0 ) : 0)
+ 1);
gas_assert (concat_string != NULL);
-
+
/* Format the thing. */
- sprintf (concat_string,
+ sprintf (concat_string,
(arity == 0 ? "%s" :
arity == 1 ? "%s:%s" :
arity == 2 ? "%s:%s:%s" :
const struct reloc_list *r)
{
fragS *f;
-
+
for (f = last_frag; f != NULL; f = f->fr_next)
if (f->fr_address <= r->u.b.r.address
&& r->u.b.r.address < f->fr_address + f->fr_fix)
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