verilog: remove unneeded import

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 009c7e1ff0b22e2ab747067fbaa847464f67eaf9..d5d878c9bf7459d495796490bcd239aa329c234e 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -5,7 +5,7 @@ from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
 from migen.fhdl.tools import *
 from migen.fhdl.bitcontainer import bits_for, flen
-from migen.fhdl.namer import Namespace, build_namespace
+from migen.fhdl.namer import build_namespace
 from migen.fhdl.conv_output import ConvOutput