.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP0R3);
InitReg(MISCREG_ICC_AP1R0_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R0);
InitReg(MISCREG_ICC_AP1R0_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R0_S);
InitReg(MISCREG_ICC_AP1R1_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R1);
InitReg(MISCREG_ICC_AP1R1_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R1_S);
InitReg(MISCREG_ICC_AP1R2_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R2);
InitReg(MISCREG_ICC_AP1R2_EL1_NS)
.bankedChild()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_AP1R2_S);
InitReg(MISCREG_ICC_AP1R3_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_AP1R3);
InitReg(MISCREG_ICC_AP1R3_EL1_NS)
.bankedChild()
return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
}
- break;
+ return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
}
case MISCREG_ICC_AP1R1:
return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
}
- break;
+ setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
+ return;
case MISCREG_ICC_AP1R1:
case MISCREG_ICC_AP1R1_EL1:
void
Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
{
- int apr_misc_reg;
- RegVal apr;
- apr_misc_reg = group == Gicv3::G0S ?
- MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
- apr = isa->readMiscRegNoEffect(apr_misc_reg);
+ int apr_misc_reg = 0;
+
+ switch (group) {
+ case Gicv3::G0S:
+ apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
+ break;
+ case Gicv3::G1S:
+ apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
+ break;
+ case Gicv3::G1NS:
+ apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS;
+ break;
+ default:
+ panic("Invalid Gicv3::GroupId");
+ }
+
+ RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
if (apr) {
apr &= apr - 1;
uint32_t prio = hppi.prio & 0xf8;
int apr_bit = prio >> (8 - PRIORITY_BITS);
int reg_bit = apr_bit % 32;
- int apr_idx = group == Gicv3::G0S ?
- MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
+
+ int apr_idx = 0;
+ switch (group) {
+ case Gicv3::G0S:
+ apr_idx = MISCREG_ICC_AP0R0_EL1;
+ break;
+ case Gicv3::G1S:
+ apr_idx = MISCREG_ICC_AP1R0_EL1_S;
+ break;
+ case Gicv3::G1NS:
+ apr_idx = MISCREG_ICC_AP1R0_EL1_NS;
+ break;
+ default:
+ panic("Invalid Gicv3::GroupId");
+ }
+
RegVal apr = isa->readMiscRegNoEffect(apr_idx);
apr |= (1 << reg_bit);
isa->setMiscRegNoEffect(apr_idx, apr);