Fixes and add comments for open FIXME items

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index cbbae7417ce4d30cdfc1e8a07168d52eb16bb325..59fdda06839f0d4b5e89e05dce62dc1f6eaa9339 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -410,13 +410,23 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
                return true;
        }
 
+       if (inst->Type() == PRIM_DLATCHRS)
+       {
+               if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
+                       module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               else
+                       module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
+                                       net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               return true;
+       }
+
        if (inst->Type() == PRIM_DFF)
        {
                VerificClocking clocking(this, inst->GetClock());
                log_assert(clocking.disable_sig == State::S0);
                log_assert(clocking.body_net == nullptr);
 
-               if (inst->GetAsyncVal()->IsGnd())
+               if (inst->GetAsyncCond()->IsGnd())
                        clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
                else
                        clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
@@ -424,6 +434,8 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
                return true;
        }
 
+       // FIXME: PRIM_DLATCH
+
        return false;
 }
 
@@ -534,6 +546,23 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
                return true;
        }
 
+       if (inst->Type() == PRIM_DFF)
+       {
+               VerificClocking clocking(this, inst->GetClock());
+               log_assert(clocking.disable_sig == State::S0);
+               log_assert(clocking.body_net == nullptr);
+
+               if (inst->GetAsyncCond()->IsGnd())
+                       cell = clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               else
+                       cell = clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
+                                       net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+               import_attributes(cell->attributes, inst);
+               return true;
+       }
+
+       // FIXME: PRIM_DLATCH
+
        #define IN  operatorInput(inst)
        #define IN1 operatorInput1(inst)
        #define IN2 operatorInput2(inst)
@@ -806,6 +835,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
                return true;
        }
 
+       // FIXME: OPER_WIDE_DLATCHSR
+
        if (inst->Type() == OPER_WIDE_DFF)
        {
                VerificClocking clocking(this, inst->GetClock());
@@ -834,6 +865,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
                return true;
        }
 
+       // FIXME: OPER_WIDE_DLATCH
+
        #undef IN
        #undef IN1
        #undef IN2