Fixed handling of parameters and localparams in functions

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index fd242fe2ee6487078c6b88d86e759446fe552709..87e8379e985dd089ffd6af1c62449a645cc2ce7b 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -520,6 +520,11 @@ struct AST_INTERNAL::ProcessGenerator
                        log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
                        break;
 
+               case AST_PARAMETER:
+               case AST_LOCALPARAM:
+                       log_error("Found parameter declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
+                       break;
+
                case AST_TCALL:
                case AST_FOR:
                        break;

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 6cda7235e11b6e9fc1c5d1870c840d12dae8bc44..24e96f074ebc28682a0d95fb873f1348ad20b651 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1013,7 +1013,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
                std::vector<AstNode*> new_children;
                for (size_t i = 0; i < children.size(); i++)
-                       if (children[i]->type == AST_WIRE) {
+                       if (children[i]->type == AST_WIRE || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) {
                                children[i]->simplify(false, false, false, stage, -1, false, false);
                                current_ast_mod->children.push_back(children[i]);
                                current_scope[children[i]->str] = children[i];
@@ -1865,7 +1865,7 @@ skip_dynamic_range_lvalue_expansion:;
                }
 
                for (auto child : decl->children)
-                       if (child->type == AST_WIRE)
+                       if (child->type == AST_WIRE || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
                        {
                                AstNode *wire = child->clone();
                                wire->str = prefix + wire->str;
@@ -1896,7 +1896,7 @@ skip_dynamic_range_lvalue_expansion:;
                        }
 
                for (auto child : decl->children)
-                       if (child->type != AST_WIRE)
+                       if (child->type != AST_WIRE && child->type != AST_PARAMETER && child->type != AST_LOCALPARAM)
                        {
                                AstNode *stmt = child->clone();
                                stmt->replace_ids(prefix, replace_rules);

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 09748eba45b4f2abc3c9217ddbf58c7c220dd621..863fee599cbbf70d55fb9b0b3d43cf38363ec956 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -963,7 +963,7 @@ simple_behavioral_stmt:
 
 // this production creates the obligatory if-else shift/reduce conflict
 behavioral_stmt:
-       defattr | assert | wire_decl |
+       defattr | assert | wire_decl | param_decl | localparam_decl |
        non_opt_delay behavioral_stmt |
        simple_behavioral_stmt ';' | ';' |
        hierarchical_id attr {

diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index 9b8e26e514c98ebe9454e7cc3e3925768d6b76a2..36ac768eacd40087c933fac7aa8002c02b26b57b 100644 (file)
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -68,7 +68,7 @@ endmodule
 
 // -------------------------------------------------------------------
 
-module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a);
+module task_func_test03(input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a);
        assign dout_a = test(din_a,din_b);
        function [7:0] test;
                input [7:0] a;
@@ -80,3 +80,32 @@ module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout
                end
        endfunction
 endmodule
+
+// -------------------------------------------------------------------
+
+module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3);
+       parameter p = 23;
+       function [7:0] test1;
+               input [7:0] i;
+               parameter p = 42;
+               begin
+                       test1 = i + p;
+               end
+       endfunction
+       function [7:0] test2;
+               input [7:0] i;
+               parameter p2 = p+42;
+               begin
+                       test2 = i + p2;
+               end
+       endfunction
+       function [7:0] test3;
+               input [7:0] i;
+               begin
+                       test3 = i + p;
+               end
+       endfunction
+       assign out1 = test1(in);
+       assign out2 = test2(in);
+       assign out3 = test3(in);
+endmodule