+2004-05-06 Randolph Chung <tausq@debian.org>
+
+ * config/pa/tm-hppa.h (RO_REGNUM, FLAGS_REGNUM, RP_REGNUM)
+ (HPPA_FP_REGNUM, HPPA_SP_REGNUM, SAR_REGNUM, IPSW_REGNUM)
+ (PCOQ_HEAD_REGNUM, PCSQ_HEAD_REGNUM, PCOQ_TAIL_REGNUM, PCSQ_TAIL_REGNUM)
+ (EIEM_REGNUM, IIR_REGNUM, ISR_REGNUM, IOR_REGNUM, SR4_REGNUM)
+ (RCR_REGNUM, PID0_REGNUM, PID1_REGNUM, PID2_REGNUM, PID3_REGNUM)
+ (CCR_REGNUM, TR0_REGNUM, CR27_REGNUM, HPPA_FP0_REGNUM, FP4_REGNUM)
+ (ARG0_REGNUM, ARG1_REGNUM, ARG2_REGNUM, ARG3_REGNUM): Move *_REGNUM
+ definitions ...
+ * hppa-tdep.h: ... to here, with HPPA_ prefix.
+ * Makefile.in (hppah-nat.o): Add $(hppa_tdep_h)
+ * hppa-hpux-tdep.c (hppa32_hpux_frame_find_saved_regs_in_sig)
+ (hppa64_hpux_frame_find_saved_regs_in_sig)
+ (child_get_current_exception_event): Add HPPA_ prefix to *_REGNUM usage.
+ * hppa-linux-nat.c (GR_REGNUM, TR_REGNUM, greg_map): Likewise.
+ * hppa-linux-tdep.c (hppa_dwarf_reg_to_regnum)
+ (hppa_linux_target_write_pc, hppa_linux_sigtramp_frame_unwind_cache)
+ (hppa_linux_sigtramp_frame_prev_register): Likewise.
+ * hppa-tdep.c (hppa32_return_value, hppa64_return_value)
+ (hppa32_push_dummy_call, hppa64_push_dummy_call, hppa64_frame_align)
+ (hppa_target_read_pc, hppa_target_write_pc, hppa_frame_cache)
+ (hppa_frame_prev_register, hppa_stub_frame_unwind_cache)
+ (hppa_stub_frame_prev_register, hppa_unwind_dummy_id)
+ (hppa_skip_permanent_breakpoint, hppa_instruction_nullified)
+ (hppa32_register_type, hppa_cannot_store_register)
+ (hppa_fetch_pointer_argument, hppa_pseudo_register_read): Likewise.
+ * hppah-nat.c (store_inferior_registers, fetch_register): Likewise.
+ * hpread.c (hpread_process_one_debug_symbol): Likewise.
+ * pa64solib.c (pa64_solib_have_load_event)
+ (pa64_solib_have_unload_event, pa64_solib_loaded_library_pathname)
+ (pa64_solib_unloaded_library_pathname): Likewise.
+ * somsolib.c (som_solib_have_load_event, som_solib_have_unload_event)
+ (som_solib_library_pathname): Likewise.
+
2004-05-05 Jim Ingham <jingham@apple.com>
* breakpoint.c (create_breakpoints): Copy the ignore count and
hpacc-abi.o: hpacc-abi.c $(defs_h) $(value_h) $(gdb_regex_h) $(gdb_string_h) \
$(gdbtypes_h) $(gdbcore_h) $(cp_abi_h)
hppah-nat.o: hppah-nat.c $(defs_h) $(inferior_h) $(target_h) $(gdbcore_h) \
- $(gdb_wait_h) $(regcache_h) $(gdb_string_h) $(infttrace_h)
+ $(gdb_wait_h) $(regcache_h) $(gdb_string_h) $(infttrace_h) \
+ $(hppa_tdep_h)
hppa-hpux-tdep.o: hppa-hpux-tdep.c $(defs_h) $(arch_utils_h) $(gdbcore_h) \
$(osabi_h) $(gdb_string_h) $(frame_h) $(hppa_tdep_h)
hppa-tdep.o: hppa-tdep.c $(defs_h) $(frame_h) $(bfd_h) $(inferior_h) \
extern int hppa_pc_requires_run_before_use (CORE_ADDR pc);
#define PC_REQUIRES_RUN_BEFORE_USE(pc) hppa_pc_requires_run_before_use (pc)
-/* Register numbers of various important registers.
- Note that some of these values are "real" register numbers,
- and correspond to the general registers of the machine,
- and some are "phony" register numbers which are too large
- to be actual register numbers as far as the user is concerned
- but do serve to get the desired values when passed to read_register. */
-
-#define R0_REGNUM 0 /* Doesn't actually exist, used as base for
- other r registers. */
-#define FLAGS_REGNUM 0 /* Various status flags */
-#define RP_REGNUM 2 /* return pointer */
-#define HPPA_FP_REGNUM 3 /* The ABI's frame pointer, when used */
-#define HPPA_SP_REGNUM 30 /* Stack pointer. */
-#define SAR_REGNUM 32 /* Shift Amount Register */
-#define IPSW_REGNUM 41 /* Interrupt Processor Status Word */
-#define PCOQ_HEAD_REGNUM 33 /* instruction offset queue head */
-#define PCSQ_HEAD_REGNUM 34 /* instruction space queue head */
-#define PCOQ_TAIL_REGNUM 35 /* instruction offset queue tail */
-#define PCSQ_TAIL_REGNUM 36 /* instruction space queue tail */
-#define EIEM_REGNUM 37 /* External Interrupt Enable Mask */
-#define IIR_REGNUM 38 /* Interrupt Instruction Register */
-#define ISR_REGNUM 39 /* Interrupt Space Register */
-#define IOR_REGNUM 40 /* Interrupt Offset Register */
-#define SR4_REGNUM 43 /* space register 4 */
-#define RCR_REGNUM 51 /* Recover Counter (also known as cr0) */
-#define PID0_REGNUM 52 /* Protection ID */
-#define PID1_REGNUM 53 /* Protection ID */
-#define PID2_REGNUM 55 /* Protection ID */
-#define PID3_REGNUM 56 /* Protection ID */
-#define CCR_REGNUM 54 /* Coprocessor Configuration Register */
-#define TR0_REGNUM 57 /* Temporary Registers (cr24 -> cr31) */
-#define CR27_REGNUM 60 /* Base register for thread-local storage, cr27 */
-#define HPPA_FP0_REGNUM 64 /* First floating-point. */
-#define FP4_REGNUM 72
-
-#define ARG0_REGNUM 26 /* The first argument of a callee. */
-#define ARG1_REGNUM 25 /* The second argument of a callee. */
-#define ARG2_REGNUM 24 /* The third argument of a callee. */
-#define ARG3_REGNUM 23 /* The fourth argument of a callee. */
-
/* PA specific macro to see if the current instruction is nullified. */
#ifndef INSTRUCTION_NULLIFIED
extern int hppa_instruction_nullified (void);
for (i = 0; i < NUM_REGS; i++)
{
- if (i == SP_REGNUM)
- fsr[SP_REGNUM] = read_memory_integer (tmp + SP_REGNUM * 4, 4);
+ if (i == HPPA_SP_REGNUM)
+ fsr[HPPA_SP_REGNUM] = read_memory_integer (tmp + HPPA_SP_REGNUM * 4, 4);
else
fsr[i] = tmp + i * 4;
}
for (i = 0; i < NUM_REGS; i++)
{
- if (i == SP_REGNUM)
- fsr[SP_REGNUM] = read_memory_integer (tmp1 + SP_REGNUM * 8, 8);
- else if (i >= FP0_REGNUM)
- fsr[i] = tmp2 + (i - FP0_REGNUM) * 8;
+ if (i == HPPA_SP_REGNUM)
+ fsr[HPPA_SP_REGNUM] = read_memory_integer (tmp1 + HPPA_SP_REGNUM * 8, 8);
+ else if (i >= HPPA_FP0_REGNUM)
+ fsr[i] = tmp2 + (i - HPPA_FP0_REGNUM) * 8;
else
fsr[i] = tmp1 + i * 8;
}
1. event kind catch or throw
2. the target address if known
3. a flag -- not sure what this is. pai/1997-07-17 */
- event_kind = read_register (ARG0_REGNUM);
- catch_addr = read_register (ARG1_REGNUM);
+ event_kind = read_register (HPPA_ARG0_REGNUM);
+ catch_addr = read_register (HPPA_ARG1_REGNUM);
/* Now go down to a user frame */
/* For a throw, __d_eh_break is called by
#include <string.h>
#include <asm/offsets.h>
+#include "hppa-tdep.h"
+
/* Prototypes for supply_gregset etc. */
#include "gregset.h"
* cr8,9,12,13
* cr10, cr15
*/
-#define GR_REGNUM(_n) (R0_REGNUM+_n)
-#define TR_REGNUM(_n) (TR0_REGNUM+_n)
+#define GR_REGNUM(_n) (HPPA_R0_REGNUM+_n)
+#define TR_REGNUM(_n) (HPPA_TR0_REGNUM+_n)
static const int greg_map[] =
{
GR_REGNUM(0), GR_REGNUM(1), GR_REGNUM(2), GR_REGNUM(3),
GR_REGNUM(24), GR_REGNUM(25), GR_REGNUM(26), GR_REGNUM(27),
GR_REGNUM(28), GR_REGNUM(29), GR_REGNUM(30), GR_REGNUM(31),
- SR4_REGNUM+1, SR4_REGNUM+2, SR4_REGNUM+3, SR4_REGNUM+4,
- SR4_REGNUM, SR4_REGNUM+5, SR4_REGNUM+6, SR4_REGNUM+7,
+ HPPA_SR4_REGNUM+1, HPPA_SR4_REGNUM+2, HPPA_SR4_REGNUM+3, HPPA_SR4_REGNUM+4,
+ HPPA_SR4_REGNUM, HPPA_SR4_REGNUM+5, HPPA_SR4_REGNUM+6, HPPA_SR4_REGNUM+7,
- PCOQ_HEAD_REGNUM, PCOQ_TAIL_REGNUM,
- PCSQ_HEAD_REGNUM, PCSQ_TAIL_REGNUM,
+ HPPA_PCOQ_HEAD_REGNUM, HPPA_PCOQ_TAIL_REGNUM,
+ HPPA_PCSQ_HEAD_REGNUM, HPPA_PCSQ_TAIL_REGNUM,
- SAR_REGNUM, IIR_REGNUM, ISR_REGNUM, IOR_REGNUM,
- IPSW_REGNUM, RCR_REGNUM,
+ HPPA_SAR_REGNUM, HPPA_IIR_REGNUM, HPPA_ISR_REGNUM, HPPA_IOR_REGNUM,
+ HPPA_IPSW_REGNUM, HPPA_RCR_REGNUM,
TR_REGNUM(0), TR_REGNUM(1), TR_REGNUM(2), TR_REGNUM(3),
TR_REGNUM(4), TR_REGNUM(5), TR_REGNUM(6), TR_REGNUM(7),
- PID0_REGNUM, PID1_REGNUM, PID2_REGNUM, PID3_REGNUM,
- CCR_REGNUM, EIEM_REGNUM,
+ HPPA_PID0_REGNUM, HPPA_PID1_REGNUM, HPPA_PID2_REGNUM, HPPA_PID3_REGNUM,
+ HPPA_CCR_REGNUM, HPPA_EIEM_REGNUM,
};
void
/* dwarf regs 32 to 85 are fpregs 4 - 31 */
if (reg >= 32 && reg <= 85)
- return FP4_REGNUM + (reg - 32);
+ return HPPA_FP4_REGNUM + (reg - 32);
warning ("Unmapped DWARF Register #%d encountered\n", reg);
return -1;
hppa_linux_target_write_pc (CORE_ADDR v, ptid_t ptid)
{
/* Probably this should be done by the kernel, but it isn't. */
- write_register_pid (PCOQ_HEAD_REGNUM, v | 0x3, ptid);
- write_register_pid (PCOQ_TAIL_REGNUM, (v + 4) | 0x3, ptid);
+ write_register_pid (HPPA_PCOQ_HEAD_REGNUM, v | 0x3, ptid);
+ write_register_pid (HPPA_PCOQ_TAIL_REGNUM, (v + 4) | 0x3, ptid);
}
/* An instruction to match. */
/* General registers. */
for (i = 1; i < 32; i++)
{
- info->saved_regs[R0_REGNUM + i].addr = scptr;
+ info->saved_regs[HPPA_R0_REGNUM + i].addr = scptr;
scptr += 4;
}
}
/* IASQ/IAOQ. */
- info->saved_regs[PCSQ_HEAD_REGNUM].addr = scptr;
+ info->saved_regs[HPPA_PCSQ_HEAD_REGNUM].addr = scptr;
scptr += 4;
- info->saved_regs[PCSQ_TAIL_REGNUM].addr = scptr;
+ info->saved_regs[HPPA_PCSQ_TAIL_REGNUM].addr = scptr;
scptr += 4;
- info->saved_regs[PCOQ_HEAD_REGNUM].addr = scptr;
+ info->saved_regs[HPPA_PCOQ_HEAD_REGNUM].addr = scptr;
scptr += 4;
- info->saved_regs[PCOQ_TAIL_REGNUM].addr = scptr;
+ info->saved_regs[HPPA_PCOQ_TAIL_REGNUM].addr = scptr;
scptr += 4;
info->base = read_memory_unsigned_integer (
{
struct hppa_linux_sigtramp_unwind_cache *info
= hppa_linux_sigtramp_frame_unwind_cache (next_frame, this_prologue_cache);
- int pcoqt = (regnum == PCOQ_TAIL_REGNUM);
+ int pcoqt = (regnum == HPPA_PCOQ_TAIL_REGNUM);
if (pcoqt)
- regnum = PCOQ_HEAD_REGNUM;
+ regnum = HPPA_PCOQ_HEAD_REGNUM;
trad_frame_prev_register (next_frame, info->saved_regs, regnum,
optimizedp, lvalp, addrp, realnump, bufferp);
/* The value always lives in the right hand end of the register
(or register pair)? */
int b;
- int reg = TYPE_CODE (type) == TYPE_CODE_FLT ? FP4_REGNUM : 28;
+ int reg = TYPE_CODE (type) == TYPE_CODE_FLT ? HPPA_FP4_REGNUM : 28;
int part = TYPE_LENGTH (type) % 4;
/* The left hand register contains only part of the value,
transfer that first so that the rest can be xfered as entire
&& TYPE_LENGTH (type) <= 8)
{
/* Floats are right aligned? */
- int offset = register_size (gdbarch, FP4_REGNUM) - TYPE_LENGTH (type);
+ int offset = register_size (gdbarch, HPPA_FP4_REGNUM) - TYPE_LENGTH (type);
if (readbuf != NULL)
- regcache_cooked_read_part (regcache, FP4_REGNUM, offset,
+ regcache_cooked_read_part (regcache, HPPA_FP4_REGNUM, offset,
TYPE_LENGTH (type), readbuf);
if (writebuf != NULL)
- regcache_cooked_write_part (regcache, FP4_REGNUM, offset,
+ regcache_cooked_write_part (regcache, HPPA_FP4_REGNUM, offset,
TYPE_LENGTH (type), writebuf);
return RETURN_VALUE_REGISTER_CONVENTION;
}
else if (TYPE_LENGTH (type) <= 8 && is_integral_type (type))
{
/* Integrals are right aligned. */
- int offset = register_size (gdbarch, FP4_REGNUM) - TYPE_LENGTH (type);
+ int offset = register_size (gdbarch, HPPA_FP4_REGNUM) - TYPE_LENGTH (type);
if (readbuf != NULL)
regcache_cooked_read_part (regcache, 28, offset,
TYPE_LENGTH (type), readbuf);
write_register (28, struct_addr);
/* Set the return address. */
- regcache_cooked_write_unsigned (regcache, RP_REGNUM, bp_addr);
+ regcache_cooked_write_unsigned (regcache, HPPA_RP_REGNUM, bp_addr);
/* Update the Stack Pointer. */
- regcache_cooked_write_unsigned (regcache, SP_REGNUM, param_end);
+ regcache_cooked_write_unsigned (regcache, HPPA_SP_REGNUM, param_end);
return param_end;
}
write_register (28, struct_addr);
/* Set the return address. */
- regcache_cooked_write_unsigned (regcache, RP_REGNUM, bp_addr);
+ regcache_cooked_write_unsigned (regcache, HPPA_RP_REGNUM, bp_addr);
/* Update the Stack Pointer. */
- regcache_cooked_write_unsigned (regcache, SP_REGNUM, param_end + 64);
+ regcache_cooked_write_unsigned (regcache, HPPA_SP_REGNUM, param_end + 64);
/* The stack will have 32 bytes of additional space for a frame marker. */
return param_end + 64;
static CORE_ADDR
hppa_target_read_pc (ptid_t ptid)
{
- int flags = read_register_pid (FLAGS_REGNUM, ptid);
+ int flags = read_register_pid (HPPA_FLAGS_REGNUM, ptid);
/* The following test does not belong here. It is OS-specific, and belongs
in native code. */
if (flags & 2)
return read_register_pid (31, ptid) & ~0x3;
- return read_register_pid (PCOQ_HEAD_REGNUM, ptid) & ~0x3;
+ return read_register_pid (HPPA_PCOQ_HEAD_REGNUM, ptid) & ~0x3;
}
/* Write out the PC. If currently in a syscall, then also write the new
static void
hppa_target_write_pc (CORE_ADDR v, ptid_t ptid)
{
- int flags = read_register_pid (FLAGS_REGNUM, ptid);
+ int flags = read_register_pid (HPPA_FLAGS_REGNUM, ptid);
/* The following test does not belong here. It is OS-specific, and belongs
in native code. */
if (flags & 2)
write_register_pid (31, v | 0x3, ptid);
- write_register_pid (PCOQ_HEAD_REGNUM, v, ptid);
- write_register_pid (PCOQ_TAIL_REGNUM, v + 4, ptid);
+ write_register_pid (HPPA_PCOQ_HEAD_REGNUM, v, ptid);
+ write_register_pid (HPPA_PCOQ_TAIL_REGNUM, v + 4, ptid);
}
/* return the alignment of a type in bytes. Structures have the maximum
if (inst == 0x6bc23fd9) /* stw rp,-0x14(sr0,sp) */
{
looking_for_rp = 0;
- cache->saved_regs[RP_REGNUM].addr = -20;
+ cache->saved_regs[HPPA_RP_REGNUM].addr = -20;
}
else if (inst == 0x0fc212c1) /* std rp,-0x10(sr0,sp) */
{
looking_for_rp = 0;
- cache->saved_regs[RP_REGNUM].addr = -16;
+ cache->saved_regs[HPPA_RP_REGNUM].addr = -16;
}
/* Check to see if we saved SP into the stack. This also
/* 1st HP CC FP register store. After this
instruction we've set enough state that the GCC and
HPCC code are both handled in the same manner. */
- cache->saved_regs[reg + FP4_REGNUM + 4].addr = 0;
+ cache->saved_regs[reg + HPPA_FP4_REGNUM + 4].addr = 0;
fp_loc = 8;
}
else
as the return register while normal code uses "rp". */
if (u->Millicode)
{
- if (trad_frame_addr_p (cache->saved_regs, RP_REGNUM))
- cache->saved_regs[PCOQ_HEAD_REGNUM] = cache->saved_regs[31];
+ if (trad_frame_addr_p (cache->saved_regs, HPPA_RP_REGNUM))
+ cache->saved_regs[HPPA_PCOQ_HEAD_REGNUM] = cache->saved_regs[31];
else
{
ULONGEST r31 = frame_unwind_register_unsigned (next_frame, 31);
- trad_frame_set_value (cache->saved_regs, PCOQ_HEAD_REGNUM, r31);
+ trad_frame_set_value (cache->saved_regs, HPPA_PCOQ_HEAD_REGNUM, r31);
}
}
else
{
- if (trad_frame_addr_p (cache->saved_regs, RP_REGNUM))
- cache->saved_regs[PCOQ_HEAD_REGNUM] = cache->saved_regs[RP_REGNUM];
+ if (trad_frame_addr_p (cache->saved_regs, HPPA_RP_REGNUM))
+ cache->saved_regs[HPPA_PCOQ_HEAD_REGNUM] = cache->saved_regs[HPPA_RP_REGNUM];
else
{
- ULONGEST rp = frame_unwind_register_unsigned (next_frame, RP_REGNUM);
- trad_frame_set_value (cache->saved_regs, PCOQ_HEAD_REGNUM, rp);
+ ULONGEST rp = frame_unwind_register_unsigned (next_frame, HPPA_RP_REGNUM);
+ trad_frame_set_value (cache->saved_regs, HPPA_PCOQ_HEAD_REGNUM, rp);
}
}
{
struct hppa_frame_cache *info = hppa_frame_cache (next_frame, this_cache);
struct gdbarch *gdbarch = get_frame_arch (next_frame);
- if (regnum == PCOQ_TAIL_REGNUM)
+ if (regnum == HPPA_PCOQ_TAIL_REGNUM)
{
/* The PCOQ TAIL, or NPC, needs to be computed from the unwound
PC register. */
*realnump = 0;
if (valuep)
{
- int regsize = register_size (gdbarch, PCOQ_HEAD_REGNUM);
+ int regsize = register_size (gdbarch, HPPA_PCOQ_HEAD_REGNUM);
CORE_ADDR pc;
int optimized;
enum lval_type lval;
int realnum;
bfd_byte value[MAX_REGISTER_SIZE];
trad_frame_prev_register (next_frame, info->saved_regs,
- PCOQ_HEAD_REGNUM, &optimized, &lval, &addr,
+ HPPA_PCOQ_HEAD_REGNUM, &optimized, &lval, &addr,
&realnum, &value);
pc = extract_unsigned_integer (&value, regsize);
store_unsigned_integer (valuep, regsize, pc + 4);
*this_cache = info;
info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
- info->saved_regs[PCOQ_HEAD_REGNUM].realreg = RP_REGNUM;
+ info->saved_regs[HPPA_PCOQ_HEAD_REGNUM].realreg = HPPA_RP_REGNUM;
info->base = frame_unwind_register_unsigned (next_frame, HPPA_SP_REGNUM);
return info;
{
struct hppa_stub_unwind_cache *info
= hppa_stub_frame_unwind_cache (next_frame, this_prologue_cache);
- int pcoqt = (regnum == PCOQ_TAIL_REGNUM);
+ int pcoqt = (regnum == HPPA_PCOQ_TAIL_REGNUM);
struct gdbarch *gdbarch = get_frame_arch (next_frame);
- int regsize = register_size (gdbarch, PCOQ_HEAD_REGNUM);
+ int regsize = register_size (gdbarch, HPPA_PCOQ_HEAD_REGNUM);
if (pcoqt)
- regnum = PCOQ_HEAD_REGNUM;
+ regnum = HPPA_PCOQ_HEAD_REGNUM;
trad_frame_prev_register (next_frame, info->saved_regs, regnum,
optimizedp, lvalp, addrp, realnump, bufferp);
static CORE_ADDR
hppa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- return frame_unwind_register_signed (next_frame, PCOQ_HEAD_REGNUM) & ~3;
+ return frame_unwind_register_signed (next_frame, HPPA_PCOQ_HEAD_REGNUM) & ~3;
}
/* Instead of this nasty cast, add a method pvoid() that prints out a
front to the back. But what do we put in the back? What
instruction comes after that one? Because of the branch delay
slot, the next insn is always at the back + 4. */
- write_register (PCOQ_HEAD_REGNUM, read_register (PCOQ_TAIL_REGNUM));
- write_register (PCSQ_HEAD_REGNUM, read_register (PCSQ_TAIL_REGNUM));
+ write_register (HPPA_PCOQ_HEAD_REGNUM, read_register (HPPA_PCOQ_TAIL_REGNUM));
+ write_register (HPPA_PCSQ_HEAD_REGNUM, read_register (HPPA_PCSQ_TAIL_REGNUM));
- write_register (PCOQ_TAIL_REGNUM, read_register (PCOQ_TAIL_REGNUM) + 4);
+ write_register (HPPA_PCOQ_TAIL_REGNUM, read_register (HPPA_PCOQ_TAIL_REGNUM) + 4);
/* We can leave the tail's space the same, since there's no jump. */
}
/* brobecker 2002/11/07: Couldn't we use a ULONGEST here? It would
avoid the type cast. I'm leaving it as is for now as I'm doing
semi-mechanical multiarching-related changes. */
- const int ipsw = (int) read_register (IPSW_REGNUM);
- const int flags = (int) read_register (FLAGS_REGNUM);
+ const int ipsw = (int) read_register (HPPA_IPSW_REGNUM);
+ const int flags = (int) read_register (HPPA_FLAGS_REGNUM);
return ((ipsw & 0x00200000) && !(flags & 0x2));
}
static struct type *
hppa32_register_type (struct gdbarch *gdbarch, int reg_nr)
{
- if (reg_nr < FP4_REGNUM)
+ if (reg_nr < HPPA_FP4_REGNUM)
return builtin_type_uint32;
else
return builtin_type_ieee_single_big;
static struct type *
hppa64_register_type (struct gdbarch *gdbarch, int reg_nr)
{
- if (reg_nr < FP4_REGNUM)
+ if (reg_nr < HPPA_FP4_REGNUM)
return builtin_type_uint64;
else
return builtin_type_ieee_double_big;
hppa_cannot_store_register (int regnum)
{
return (regnum == 0
- || regnum == PCSQ_HEAD_REGNUM
- || (regnum >= PCSQ_TAIL_REGNUM && regnum < IPSW_REGNUM)
- || (regnum > IPSW_REGNUM && regnum < FP4_REGNUM));
+ || regnum == HPPA_PCSQ_HEAD_REGNUM
+ || (regnum >= HPPA_PCSQ_TAIL_REGNUM && regnum < HPPA_IPSW_REGNUM)
+ || (regnum > HPPA_IPSW_REGNUM && regnum < HPPA_FP4_REGNUM));
}
struct type *type)
{
CORE_ADDR addr;
- get_frame_register (frame, R0_REGNUM + 26 - argi, &addr);
+ get_frame_register (frame, HPPA_R0_REGNUM + 26 - argi, &addr);
return addr;
}
ULONGEST tmp;
regcache_raw_read_unsigned (regcache, regnum, &tmp);
- if (regnum == PCOQ_HEAD_REGNUM || regnum == PCOQ_TAIL_REGNUM)
+ if (regnum == HPPA_PCOQ_HEAD_REGNUM || regnum == HPPA_PCOQ_TAIL_REGNUM)
tmp &= ~0x3;
store_unsigned_integer (buf, sizeof(tmp), tmp);
}
enum { HPPA_INSTRUCTION_SIZE = 4 };
+/* Register numbers of various important registers.
+ Note that some of these values are "real" register numbers,
+ and correspond to the general registers of the machine,
+ and some are "phony" register numbers which are too large
+ to be actual register numbers as far as the user is concerned
+ but do serve to get the desired values when passed to read_register. */
+
+enum {
+ HPPA_R0_REGNUM = 0, /* Doesn't actually exist, used as base for
+ other r registers. */
+ HPPA_FLAGS_REGNUM = 0, /* Various status flags */
+ HPPA_RP_REGNUM = 2, /* return pointer */
+ HPPA_FP_REGNUM = 3, /* The ABI's frame pointer, when used */
+ HPPA_SP_REGNUM = 30, /* Stack pointer. */
+ HPPA_SAR_REGNUM = 32, /* Shift Amount Register */
+ HPPA_IPSW_REGNUM = 41, /* Interrupt Processor Status Word */
+ HPPA_PCOQ_HEAD_REGNUM = 33, /* instruction offset queue head */
+ HPPA_PCSQ_HEAD_REGNUM = 34, /* instruction space queue head */
+ HPPA_PCOQ_TAIL_REGNUM = 35, /* instruction offset queue tail */
+ HPPA_PCSQ_TAIL_REGNUM = 36, /* instruction space queue tail */
+ HPPA_EIEM_REGNUM = 37, /* External Interrupt Enable Mask */
+ HPPA_IIR_REGNUM = 38, /* Interrupt Instruction Register */
+ HPPA_ISR_REGNUM = 39, /* Interrupt Space Register */
+ HPPA_IOR_REGNUM = 40, /* Interrupt Offset Register */
+ HPPA_SR4_REGNUM = 43, /* space register 4 */
+ HPPA_RCR_REGNUM = 51, /* Recover Counter (also known as cr0) */
+ HPPA_PID0_REGNUM = 52, /* Protection ID */
+ HPPA_PID1_REGNUM = 53, /* Protection ID */
+ HPPA_PID2_REGNUM = 55, /* Protection ID */
+ HPPA_PID3_REGNUM = 56, /* Protection ID */
+ HPPA_CCR_REGNUM = 54, /* Coprocessor Configuration Register */
+ HPPA_TR0_REGNUM = 57, /* Temporary Registers (cr24 -> cr31) */
+ HPPA_CR27_REGNUM = 60, /* Base register for thread-local storage, cr27 */
+ HPPA_FP0_REGNUM = 64, /* First floating-point. */
+ HPPA_FP4_REGNUM = 72,
+
+ HPPA_ARG0_REGNUM = 26, /* The first argument of a callee. */
+ HPPA_ARG1_REGNUM = 25, /* The second argument of a callee. */
+ HPPA_ARG2_REGNUM = 24, /* The third argument of a callee. */
+ HPPA_ARG3_REGNUM = 23 /* The fourth argument of a callee. */
+};
+
/* Target-dependent structure in gdbarch. */
struct gdbarch_tdep
{
#include "infttrace.h"
#include <signal.h>
+#include "hppa-tdep.h"
static CORE_ADDR text_end;
}
/* Floating-point registers come from the ss_fpblock area. */
- else if (regno >= FP0_REGNUM)
+ else if (regno >= HPPA_FP0_REGNUM)
addr = (HPPAH_OFFSETOF (save_state_t, ss_fpblock)
- + (DEPRECATED_REGISTER_BYTE (regno) - DEPRECATED_REGISTER_BYTE (FP0_REGNUM)));
+ + (DEPRECATED_REGISTER_BYTE (regno) - DEPRECATED_REGISTER_BYTE (HPPA_FP0_REGNUM)));
/* Wide registers come from the ss_wide area.
I think it's more PC to test (ss_flags & SS_WIDEREGS) to select
layering will not allow us to perform a 64bit register store.
What a crock. */
- if (regno == PCOQ_HEAD_REGNUM || regno == PCOQ_TAIL_REGNUM && len == 8)
+ if (regno == HPPA_PCOQ_HEAD_REGNUM || regno == HPPA_PCOQ_TAIL_REGNUM && len == 8)
{
CORE_ADDR temp;
/* Another crock. HPUX complains if you write a nonzero value to
the high part of IPSW. What will it take for HP to catch a
clue about building sensible interfaces? */
- if (regno == IPSW_REGNUM && len == 8)
+ if (regno == HPPA_IPSW_REGNUM && len == 8)
*(int *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (regno)] = 0;
#endif
REGISTER_NAME (regno), err);
/* If we fail to write the PC, give a true error instead of
just a warning. */
- if (regno == PCOQ_HEAD_REGNUM || regno == PCOQ_TAIL_REGNUM)
+ if (regno == HPPA_PCOQ_HEAD_REGNUM || regno == HPPA_PCOQ_TAIL_REGNUM)
perror_with_name (msg);
else
warning (msg);
}
/* Floating-point registers come from the ss_fpblock area. */
- else if (regno >= FP0_REGNUM)
+ else if (regno >= HPPA_FP0_REGNUM)
addr = (HPPAH_OFFSETOF (save_state_t, ss_fpblock)
- + (DEPRECATED_REGISTER_BYTE (regno) - DEPRECATED_REGISTER_BYTE (FP0_REGNUM)));
+ + (DEPRECATED_REGISTER_BYTE (regno) - DEPRECATED_REGISTER_BYTE (HPPA_FP0_REGNUM)));
/* Wide registers come from the ss_wide area.
I think it's more PC to test (ss_flags & SS_WIDEREGS) to select
/* If we're reading an address from the instruction address queue,
mask out the bottom two bits --- they contain the privilege
level. */
- if (regno == PCOQ_HEAD_REGNUM || regno == PCOQ_TAIL_REGNUM)
+ if (regno == HPPA_PCOQ_HEAD_REGNUM || regno == HPPA_PCOQ_TAIL_REGNUM)
buf[len - 1] &= ~0x3;
supply_register (regno, buf);
/* Thread-local variable.
*/
SYMBOL_CLASS (sym) = LOC_HP_THREAD_LOCAL_STATIC;
- SYMBOL_BASEREG (sym) = CR27_REGNUM;
+ SYMBOL_BASEREG (sym) = HPPA_CR27_REGNUM;
if (objfile->flags & OBJF_SHARED)
{
{
CORE_ADDR event_kind;
- event_kind = read_register (ARG0_REGNUM);
+ event_kind = read_register (HPPA_ARG0_REGNUM);
return (event_kind == DLD_CB_LOAD);
}
{
CORE_ADDR event_kind;
- event_kind = read_register (ARG0_REGNUM);
+ event_kind = read_register (HPPA_ARG0_REGNUM);
return (event_kind == DLD_CB_UNLOAD);
}
pa64_solib_loaded_library_pathname (int pid)
{
static char dll_path[MAXPATHLEN];
- CORE_ADDR dll_path_addr = read_register (ARG3_REGNUM);
+ CORE_ADDR dll_path_addr = read_register (HPPA_ARG3_REGNUM);
read_memory_string (dll_path_addr, dll_path, MAXPATHLEN);
return dll_path;
}
pa64_solib_unloaded_library_pathname (int pid)
{
static char dll_path[MAXPATHLEN];
- CORE_ADDR dll_path_addr = read_register (ARG3_REGNUM);
+ CORE_ADDR dll_path_addr = read_register (HPPA_ARG3_REGNUM);
read_memory_string (dll_path_addr, dll_path, MAXPATHLEN);
return dll_path;
}
{
CORE_ADDR event_kind;
- event_kind = read_register (ARG0_REGNUM);
+ event_kind = read_register (HPPA_ARG0_REGNUM);
return (event_kind == SHL_LOAD);
}
{
CORE_ADDR event_kind;
- event_kind = read_register (ARG0_REGNUM);
+ event_kind = read_register (HPPA_ARG0_REGNUM);
return (event_kind == SHL_UNLOAD);
}
static char dll_pathname[1024];
/* Read the descriptor of this newly-loaded library. */
- dll_handle_address = read_register (ARG1_REGNUM);
+ dll_handle_address = read_register (HPPA_ARG1_REGNUM);
read_memory (dll_handle_address, (char *) &dll_descriptor, sizeof (dll_descriptor));
/* We can find a pointer to the dll's pathname within the descriptor. */
projects / binutils-gdb.git / commitdiff