MSVC cannot omit operand in conditional

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index b34a62248f27f4b561309d495bd83a38f3328423..15c231f3b98b1b02f4724b0b2df14ced514259a5 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1481,7 +1481,7 @@ enum_name_decl:
                delete $1;
                SET_AST_NODE_LOC(node, @1, @1);
                delete node->children[0];
-               node->children[0] = $2 ?: new AstNode(AST_NONE);
+               node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
                astbuf2->children.push_back(node);
        }
        ;