Fixed memory_bram for ROMs in BRAMs with write-enable inputs

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 824d6a6e822d3ba3291bcf97e8f8a3e5352bdc4a..f638b5bb799120888278e4ab7401169d97d9cd58 100644 (file)
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -433,7 +433,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
        SigSpec rd_data = cell->getPort("\\RD_DATA");
        SigSpec rd_addr = cell->getPort("\\RD_ADDR");
 
-       if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0)
+       if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
        {
                int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable;
                log("      Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size);