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ac: update register and packet definitions for preemption
authorMarek Olšák <marek.olsak@amd.com>
Wed, 5 Feb 2020 21:55:41 +0000 (16:55 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Sat, 23 May 2020 07:45:07 +0000 (03:45 -0400)
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

src/amd/common/sid.h patch | blob | history
src/amd/registers/amdgfxregs.json patch | blob | history
src/amd/registers/gfx10.json patch | blob | history
src/amd/vulkan/radv_cmd_buffer.c patch | blob | history
src/amd/vulkan/radv_device.c patch | blob | history
src/amd/vulkan/radv_sqtt.c patch | blob | history
src/amd/vulkan/si_cmd_buffer.c patch | blob | history
src/gallium/drivers/radeonsi/si_state.c patch | blob | history

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 387689876d10c6fa76f8e321cc4fd689380d4b5d..1f54f94ae7b7f2f106eac838dda6d278ce53baba 100644 (file)
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -32,9 +32,10 @@
 #define SI_SH_REG_OFFSET                     0x0000B000
 #define SI_SH_REG_END                        0x0000C000
 #define SI_CONTEXT_REG_OFFSET                0x00028000
-#define SI_CONTEXT_REG_END                   0x00029000
+#define SI_CONTEXT_REG_END                   0x00030000
 #define CIK_UCONFIG_REG_OFFSET               0x00030000
-#define CIK_UCONFIG_REG_END                  0x00038000
+#define CIK_UCONFIG_REG_END                  0x00040000
+
 
 #define EVENT_TYPE_CACHE_FLUSH                  0x6
 #define EVENT_TYPE_PS_PARTIAL_FLUSH            0x10
@@ -100,9 +101,19 @@
 #define PKT3_INDEX_BASE                        0x26
 #define PKT3_DRAW_INDEX_2                      0x27
 #define PKT3_CONTEXT_CONTROL                   0x28
-#define     CONTEXT_CONTROL_LOAD_ENABLE(x)     (((unsigned)(x) & 0x1) << 31)
-#define     CONTEXT_CONTROL_LOAD_CE_RAM(x)     (((unsigned)(x) & 0x1) << 28)
-#define     CONTEXT_CONTROL_SHADOW_ENABLE(x)   (((unsigned)(x) & 0x1) << 31)
+#define     CC0_LOAD_GLOBAL_CONFIG(x)          (((unsigned)(x) & 0x1) << 0)
+#define     CC0_LOAD_PER_CONTEXT_STATE(x)      (((unsigned)(x) & 0x1) << 1)
+#define     CC0_LOAD_GLOBAL_UCONFIG(x)         (((unsigned)(x) & 0x1) << 15)
+#define     CC0_LOAD_GFX_SH_REGS(x)            (((unsigned)(x) & 0x1) << 16)
+#define     CC0_LOAD_CS_SH_REGS(x)             (((unsigned)(x) & 0x1) << 24)
+#define     CC0_LOAD_CE_RAM(x)                 (((unsigned)(x) & 0x1) << 28)
+#define     CC0_UPDATE_LOAD_ENABLES(x)         (((unsigned)(x) & 0x1) << 31)
+#define     CC1_SHADOW_GLOBAL_CONFIG(x)        (((unsigned)(x) & 0x1) << 0)
+#define     CC1_SHADOW_PER_CONTEXT_STATE(x)    (((unsigned)(x) & 0x1) << 1)
+#define     CC1_SHADOW_GLOBAL_UCONFIG(x)       (((unsigned)(x) & 0x1) << 15)
+#define     CC1_SHADOW_GFX_SH_REGS(x)          (((unsigned)(x) & 0x1) << 16)
+#define     CC1_SHADOW_CS_SH_REGS(x)           (((unsigned)(x) & 0x1) << 24)
+#define     CC1_UPDATE_SHADOW_ENABLES(x)       (((unsigned)(x) & 0x1) << 31)
 #define PKT3_INDEX_TYPE                        0x2A /* not on GFX9 */
 #define PKT3_DRAW_INDIRECT_MULTI               0x2C
 #define   R_2C3_DRAW_INDEX_LOC                  0x2C3
@@ -185,6 +196,9 @@
 #define PKT3_ONE_REG_WRITE                     0x57 /* not on CIK */
 #define PKT3_ACQUIRE_MEM                       0x58 /* new for CIK */
 #define PKT3_REWIND                            0x59 /* VI+ [any ring] or CIK [compute ring only] */
+#define PKT3_LOAD_UCONFIG_REG                  0x5E /* GFX7+ */
+#define PKT3_LOAD_SH_REG                       0x5F
+#define PKT3_LOAD_CONTEXT_REG                  0x61
 #define PKT3_SET_CONFIG_REG                    0x68
 #define PKT3_SET_CONTEXT_REG                   0x69
 #define PKT3_SET_SH_REG                        0x76
@@ -198,7 +212,7 @@
 #define PKT3_INCREMENT_DE_COUNTER              0x85
 #define PKT3_WAIT_ON_CE_COUNTER                0x86
 #define PKT3_SET_SH_REG_INDEX                  0x9B
-#define PKT3_LOAD_CONTEXT_REG                  0x9F /* new for VI */
+#define PKT3_LOAD_CONTEXT_REG_INDEX            0x9F /* new for VI */
 
 #define PKT_TYPE_S(x)                   (((unsigned)(x) & 0x3) << 30)
 #define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
diff --git a/src/amd/registers/amdgfxregs.json b/src/amd/registers/amdgfxregs.json
index ecfc8bc7a67e063a185443bc46b0d01f7019105a..b58d0ca7198ab67b1b8fca40344d230d5616dd5f 100644 (file)
--- a/src/amd/registers/amdgfxregs.json
+++ b/src/amd/registers/amdgfxregs.json
@@ -3288,6 +3288,11 @@
    "name": "COMPUTE_WAVE_RESTORE_CONTROL",
    "type_ref": "COMPUTE_WAVE_RESTORE_CONTROL"
   },
+  {
+   "chips": ["gfx9"],
+   "map": {"at": 47252, "to": "mm"},
+   "name": "COMPUTE_SHADER_CHKSUM"
+  },
   {
    "chips": ["gfx9"],
    "map": {"at": 213048, "to": "mm"},
@@ -6258,6 +6263,11 @@
    "name": "PA_SC_SCREEN_EXTENT_MAX_1",
    "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
   },
+  {
+   "chips": ["gfx9"],
+   "map": {"at": 199380, "to": "mm"},
+   "name": "PA_STATE_STEREO_X"
+  },
   {
    "chips": ["gfx7", "fiji", "gfx9", "stoney", "gfx8"],
    "map": {"at": 199872, "to": "mm"},
diff --git a/src/amd/registers/gfx10.json b/src/amd/registers/gfx10.json
index 93351ad19436b60bbba356440ae4d2153089e979..08f111c87c7d548252620601fa4e5cc3c41dffdf 100644 (file)
--- a/src/amd/registers/gfx10.json
+++ b/src/amd/registers/gfx10.json
@@ -7817,26 +7817,26 @@
   {
    "chips": ["gfx10"],
    "map": {"at": 47248, "to": "mm"},
-   "name": "COMPUTE_PREF_PRI_ACCUM_0",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "COMPUTE_USER_ACCUM_0",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 47252, "to": "mm"},
-   "name": "COMPUTE_PREF_PRI_ACCUM_1",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "COMPUTE_USER_ACCUM_1",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 47256, "to": "mm"},
-   "name": "COMPUTE_PREF_PRI_ACCUM_2",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "COMPUTE_USER_ACCUM_2",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 47260, "to": "mm"},
-   "name": "COMPUTE_PREF_PRI_ACCUM_3",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "COMPUTE_USER_ACCUM_3",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
@@ -14429,98 +14429,98 @@
   {
    "chips": ["gfx10"],
    "map": {"at": 45768, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_0",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45772, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_1",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45776, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_2",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45780, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_3",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 46280, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_0",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 46284, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_1",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 46288, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_2",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 46292, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_3",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45256, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_0",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_PS_0",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45260, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_1",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_PS_1",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45264, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_2",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_PS_2",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45268, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_3",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_PS_3",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45512, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_0",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_VS_0",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45516, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_1",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_VS_1",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45520, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_2",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_VS_2",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
    "map": {"at": 45524, "to": "mm"},
-   "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_3",
-   "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+   "name": "SPI_SHADER_USER_ACCUM_VS_3",
+   "type_ref": "COMPUTE_USER_ACCUM_0"
   },
   {
    "chips": ["gfx10"],
@@ -17594,14 +17594,9 @@
     {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
    ]
   },
-  "COMPUTE_PREF_PRI_ACCUM_0": {
+  "COMPUTE_USER_ACCUM_0": {
    "fields": [
-    {"bits": [0, 2], "name": "COEFFICIENT_HIER_SELECT"},
-    {"bits": [3, 5], "name": "CONTRIBUTION_HIER_SELECT"},
-    {"bits": [6, 6], "name": "GROUP_UPDATE_EN"},
-    {"bits": [7, 7], "name": "RESERVED"},
-    {"bits": [8, 15], "name": "COEFFICIENT"},
-    {"bits": [16, 23], "name": "CONTRIBUTION"}
+    {"bits": [0, 6], "name": "CONTRIBUTION"}
    ]
   },
   "COMPUTE_PREF_PRI_CNTR_CTRL": {
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 896bb63b08ca8228aba426cf0f412124c60e72bc..1c2784bdeeac190e7e7c8426157b95fd3f03ea3c 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1812,7 +1812,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
        uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
 
        if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
-               radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
+               radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
                radeon_emit(cs, va);
                radeon_emit(cs, va >> 32);
                radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
@@ -1996,7 +1996,7 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
        uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
 
        if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
-               radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
+               radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
                radeon_emit(cs, va);
                radeon_emit(cs, va >> 32);
                radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5855e63ca2f7f6a8fe83aee1984d925c99a485a6..e8f6bf818c31519dcca114a9f7b23dd7b0084ee8 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3222,8 +3222,8 @@ VkResult radv_CreateDevice(
                switch (family) {
                case RADV_QUEUE_GENERAL:
                        radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
-                       radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
-                       radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
+                       radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
+                       radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
                        break;
                case RADV_QUEUE_COMPUTE:
                        radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c
index 1935c990255354e61992a78e01fb06f18866cad1..e135e0c02cccc067a8d942f17f69ada01354a1f9 100644 (file)
--- a/src/amd/vulkan/radv_sqtt.c
+++ b/src/amd/vulkan/radv_sqtt.c
@@ -408,8 +408,8 @@ radv_thread_trace_init_cs(struct radv_device *device)
                switch (family) {
                case RADV_QUEUE_GENERAL:
                        radeon_emit(device->thread_trace_start_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
-                       radeon_emit(device->thread_trace_start_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
-                       radeon_emit(device->thread_trace_start_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
+                       radeon_emit(device->thread_trace_start_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
+                       radeon_emit(device->thread_trace_start_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
                        break;
                case RADV_QUEUE_COMPUTE:
                        radeon_emit(device->thread_trace_start_cs[family], PKT3(PKT3_NOP, 0, 0));
@@ -443,8 +443,8 @@ radv_thread_trace_init_cs(struct radv_device *device)
                switch (family) {
                case RADV_QUEUE_GENERAL:
                        radeon_emit(device->thread_trace_stop_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
-                       radeon_emit(device->thread_trace_stop_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
-                       radeon_emit(device->thread_trace_stop_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
+                       radeon_emit(device->thread_trace_stop_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
+                       radeon_emit(device->thread_trace_stop_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
                        break;
                case RADV_QUEUE_COMPUTE:
                        radeon_emit(device->thread_trace_stop_cs[family], PKT3(PKT3_NOP, 0, 0));
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index ad71ee55ac279b33b707d790ebef59b3c38510fb..28ca8560c09be7c39b6580ae751198842646effd 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -164,8 +164,8 @@ si_emit_graphics(struct radv_device *device,
        int i;
 
        radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
-       radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
-       radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
+       radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
+       radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
 
        if (has_clear_state) {
                radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 75f439b48cfda6ed9a8f070bd0975bb4c88e8320..df39a05403b16a6dd0c3a6843f4a4a89fccc035a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5155,8 +5155,8 @@ static void si_init_config(struct si_context *sctx)
       return;
 
    si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
-   si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
-   si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
+   si_pm4_cmd_add(pm4, CC0_UPDATE_LOAD_ENABLES(1));
+   si_pm4_cmd_add(pm4, CC1_UPDATE_SHADOW_ENABLES(1));
    si_pm4_cmd_end(pm4, false);
 
    if (has_clear_state) {