Changed bitmap format images to svg vector format

i_o_io_tristate_jtag
gpio-block
jtag-block

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 0ad09eb5ef47fc82eb9b0ec9f260716df5b02aad..c603e0357571d59acc37b705134a84a4b426d637 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -216,8 +216,7 @@ and triaging of faults.
   pad is working.  If the UART Rx peripheral was faulty
   this would not be possible.
 
-<img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
-  width=500 />
+[[!img jtag-block.svg ]]
 
 ## C4M JTAG TAP
 
@@ -411,7 +410,7 @@ there will be a lag on the output data compared to the incoming
 
 # Pinmux GPIO Block
 The following diagram is an example of a GPIO block with switchable banks and comes from the Ericson presentation on a GPIO architecture.
-[[!img gpio_block.png size="600x"]]
+[[!img gpio-block.svg ]]
 
 The block we are developing is very similar, but is lacking some of configuration of the former (due to complexity and time constraints).
 
@@ -547,5 +546,5 @@ The diagrams below show 1-bit GPIO connectivity, as well as the 4-bit case.
 
 Diagram constructed from the nmigen plat.py file.
 
-[[!img i_o_io_tristate_jtag.JPG size="600x"]]
+[[!img i_o_io_tristate_jtag.svg ]]