soc: allow passing custom CPU class to SoC.

Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 11e8dd2b2f55285ec3ce99cba9a0b327ffff1b66..d22989a208cf1bfc232581c885dfcc6ed640306e 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -762,7 +762,7 @@ class SoC(Module):
         self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
         self.add_config("CSR_ALIGNMENT",  self.csr.alignment)
 
-    def add_cpu(self, name="vexriscv", variant="standard", reset_address=None):
+    def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None):
         if name not in cpu.CPUS.keys():
             self.logger.error("{} CPU {}, supporteds: {}".format(
                 colorer(name),
@@ -770,7 +770,8 @@ class SoC(Module):
                 colorer(", ".join(cpu.CPUS.keys()))))
             raise
         # Add CPU
-        self.submodules.cpu = cpu.CPUS[name](self.platform, variant)
+        cpu_cls = cls if cls is not None else cpu.CPUS[name]
+        self.submodules.cpu = cpu_cls(self.platform, variant)
         # Update SoC with CPU constraints
         for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
             self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 3eb0016c70560ec2d71809c154cb07b8ca3d617c..f61555a313801b3b712b91d1db0fcf9da718c5be 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -65,6 +65,7 @@ class SoCCore(LiteXSoC):
         cpu_type                 = "vexriscv",
         cpu_reset_address        = None,
         cpu_variant              = None,
+        cpu_cls                  = None,
         # ROM parameters
         integrated_rom_size      = 0,
         integrated_rom_init      = [],
@@ -131,6 +132,7 @@ class SoCCore(LiteXSoC):
 
         self.cpu_type                   = cpu_type
         self.cpu_variant                = cpu_variant
+        self.cpu_cls                    = cpu_cls
 
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
@@ -154,6 +156,7 @@ class SoCCore(LiteXSoC):
         self.add_cpu(
             name          = str(cpu_type),
             variant       = "standard" if cpu_variant is None else cpu_variant,
+            cls           = cpu_cls,
             reset_address = None if integrated_rom_size else cpu_reset_address)
 
         # Add User's interrupts