consecutive multiply-add instruction doesn't depend on the previous write
register.
+# SVP64 instructions implementing matrix multiply
+
+* SVP64 assembler example:
+[unit test](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;hb=30f2d8a8e92ad2939775f19e6a0f387499e9842b#l56)
+* SVREMAP and SVSHAPE instructions defined in:
+[[/openpower/sv/rfc/ls009|LS009 RFC]]
+* Multiple-Add Low Doubleword instruction pseudo-code (OpenPOWER ISA 3.0C
+Book I, section 3.3.9): [[/openpower/isa/fixedarith|]]
+
+*(Need to check if first arg of svremap correct, then one shown works with
+ISACaller)*
+
+ svshape 2, 2, 3, 0, 0
+ svremap 31, 1, 2, 3, 0, 0, 0
+ sv.maddld *0, *16, *32, *0
+
+## svshape
+
+
+
+## SVREMAP
+
+
## Appendix
+
### Links
- [Online matrix calculator](https://matrix.reshish.com/multCalculation.php)