(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index f0b6b86646988a62f9c10a872ff9cec35520d6c0..35ef65f2238cfe6bacd6af2824f2ab295a2f3376 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -882,7 +882,10 @@ ZOLC capability in order to compact binary size to the bare minimum.
 
 One key strategic question does remain: do the PEs need to have
 a RADIX MMU and associated TLB-aware minimal L1 Cache, in order
-to support OpenCAPI properly?
+to support OpenCAPI properly? The saving grace here is that with
+the expectation of running only hot-loops with ZOLC-driven
+binaries, the size of L1 Cache needed would be miniscule compared
+to the average high-end CPU.
 
 **Roadmap summary of Advanced SVP64**