i965: Fix the gen6 jump size for BREAK/CONT in new FS.

Since gen5, jumps are in increments of 64 bits instead of increments
of 128-bit instructions.

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 864c0b91e5bf32744162291f79903c8925cd5279..1968e7fde0e759d89033f41112986e30e0a79181 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2518,7 +2518,7 @@ fs_visitor::generate_code()
         struct brw_instruction *inst0, *inst1;
         GLuint br = 1;
 
-        if (intel->gen == 5)
+        if (intel->gen >= 5)
            br = 2;
 
         assert(loop_stack_depth > 0);