+2020-06-22 Alex Coplan <alex.coplan@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_SHA2): Normalize.
+ (AARCH64_FEATURE_AES): Likewise.
+ (AARCH64_FEATURE_V8_4): Likewise.
+ (AARCH64_FEATURE_SM4): Likewise.
+ (AARCH64_FEATURE_SHA3): Likewise.
+ (AARCH64_FEATURE_V8): Likewise.
+ (AARCH64_FEATURE_V8_2): Likewise.
+ (AARCH64_FEATURE_V8_3): Likewise.
+ (AARCH64_FEATURE_FP): Likewise.
+ (AARCH64_FEATURE_SIMD): Likewise.
+ (AARCH64_FEATURE_CRC): Likewise.
+ (AARCH64_FEATURE_LSE): Likewise.
+ (AARCH64_FEATURE_PAN): Likewise.
+ (AARCH64_FEATURE_LOR): Likewise.
+ (AARCH64_FEATURE_RDMA): Likewise.
+ (AARCH64_FEATURE_V8_1): Likewise.
+ (AARCH64_FEATURE_F16): Likewise.
+ (AARCH64_FEATURE_RAS): Likewise.
+ (AARCH64_FEATURE_PROFILE): Likewise.
+ (AARCH64_FEATURE_SVE): Likewise.
+ (AARCH64_FEATURE_RCPC): Likewise.
+ (AARCH64_FEATURE_COMPNUM): Likewise.
+ (AARCH64_FEATURE_DOTPROD): Likewise.
+ (AARCH64_FEATURE_F16_FML): Likewise.
+ (AARCH64_FEATURE_V8_5): Likewise.
+ (AARCH64_FEATURE_V8_6): Likewise.
+ (AARCH64_FEATURE_BFLOAT16): Likewise.
+ (AARCH64_FEATURE_FLAGMANIP): Likewise.
+ (AARCH64_FEATURE_FRINTTS): Likewise.
+ (AARCH64_FEATURE_SB): Likewise.
+ (AARCH64_FEATURE_PREDRES): Likewise.
+ (AARCH64_FEATURE_CVADP): Likewise.
+ (AARCH64_FEATURE_RNG): Likewise.
+ (AARCH64_FEATURE_BTI): Likewise.
+ (AARCH64_FEATURE_SCXTNUM): Likewise.
+ (AARCH64_FEATURE_ID_PFR2): Likewise.
+ (AARCH64_FEATURE_SSBS): Likewise.
+ (AARCH64_FEATURE_MEMTAG): Likewise.
+ (AARCH64_FEATURE_TME): Likewise.
+ (AARCH64_FEATURE_I8MM): Likewise.
+ (AARCH64_FEATURE_F32MM): Likewise.
+ (AARCH64_FEATURE_F64MM): Likewise.
+ (AARCH64_FEATURE_SVE2): Likewise.
+ (AARCH64_FEATURE_SVE2_AES): Likewise.
+ (AARCH64_FEATURE_SVE2_BITPERM): Likewise.
+ (AARCH64_FEATURE_SVE2_SM4): Likewise.
+ (AARCH64_FEATURE_SVE2_SHA3): Likewise.
+
2020-06-22 Saagar Jha <saagar@saagarjha.com>
* mach-o/loader.h: Add declarations of two new Mach-O load
typedef uint32_t aarch64_insn;
/* The following bitmasks control CPU features. */
-#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
-#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
-#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
-#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
-#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
-#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
-#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
-#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
-#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
-#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
-#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
-#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
-#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
-#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
-#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
-#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
-#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
-#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
-#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
-#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
-#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
-#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
-#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
-#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
-#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
-#define AARCH64_FEATURE_V8_6 0x00000002 /* ARMv8.6 processors. */
-#define AARCH64_FEATURE_BFLOAT16 0x00000004 /* Bfloat16 insns. */
-
-/* Flag Manipulation insns. */
-#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
-/* FRINT[32,64][Z,X] insns. */
-#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
-/* SB instruction. */
-#define AARCH64_FEATURE_SB 0x10000000000ULL
-/* Execution and Data Prediction Restriction instructions. */
-#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
-/* DC CVADP. */
-#define AARCH64_FEATURE_CVADP 0x40000000000ULL
-/* Random Number instructions. */
-#define AARCH64_FEATURE_RNG 0x80000000000ULL
-/* BTI instructions. */
-#define AARCH64_FEATURE_BTI 0x100000000000ULL
-/* SCXTNUM_ELx. */
-#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
-/* ID_PFR2 instructions. */
-#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
-/* SSBS mechanism enabled. */
-#define AARCH64_FEATURE_SSBS 0x800000000000ULL
-/* Memory Tagging Extension. */
-#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
-/* Transactional Memory Extension. */
-#define AARCH64_FEATURE_TME 0x2000000000000ULL
-
-/* Matrix Multiply instructions */
-#define AARCH64_FEATURE_I8MM 0x10000000000000ULL
-#define AARCH64_FEATURE_F32MM 0x20000000000000ULL
-#define AARCH64_FEATURE_F64MM 0x40000000000000ULL
-
-/* SVE2 instructions. */
-#define AARCH64_FEATURE_SVE2 0x000000010
-#define AARCH64_FEATURE_SVE2_AES 0x000000080
-#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100
-#define AARCH64_FEATURE_SVE2_SM4 0x000000200
-#define AARCH64_FEATURE_SVE2_SHA3 0x000000400
+#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
+#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
+#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
+#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
+#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
+#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
+#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
+#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
+#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
+#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
+#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
+#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
+#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
+#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
+#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
+#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
+#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
+#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
+#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
+#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
+#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
+#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
+#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
+#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
+#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
+#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
+#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
+#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
+#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
+#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
+#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
+#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
+#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
+#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
+#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
+#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
+#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
+#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
+#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
+#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
+#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
+#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
+#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
+#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
+#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
+#define AARCH64_FEATURE_F32MM (1ULL << 53)
+#define AARCH64_FEATURE_F64MM (1ULL << 54)
/* Crypto instructions are the combination of AES and SHA2. */
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
projects / binutils-gdb.git / commitdiff