TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
-
- VirtualPort *getVirtPort()
- { return actualTC->getVirtPort(); }
#else
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
+ VirtualPort *getVirtPort()
+ { return actualTC->getVirtPort(); }
+
FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
Status status() const { return actualTC->status(); }
using namespace TheISA;
-#if FULL_SYSTEM
-
VirtualPort *
InOrderThreadContext::getVirtPort()
{
return thread->getVirtPort();
}
+#if FULL_SYSTEM
void
InOrderThreadContext::dumpFuncProfile()
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
- VirtualPort *getVirtPort();
-
void connectMemPorts(ThreadContext *tc)
{ thread->connectMemPorts(tc); }
Process *getProcessPtr() { return thread->getProcessPtr(); }
#endif
+ VirtualPort *getVirtPort();
FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
/** Returns this thread's status. */
virtual TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
- virtual VirtualPort *getVirtPort();
-
virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
#else
virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
#endif
+ virtual VirtualPort *getVirtPort();
+
virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
/** Returns this thread's status. */
#include "cpu/quiesce_event.hh"
#include "debug/O3CPU.hh"
-#if FULL_SYSTEM
template <class Impl>
VirtualPort *
O3ThreadContext<Impl>::getVirtPort()
return thread->getVirtPort();
}
+#if FULL_SYSTEM
template <class Impl>
void
O3ThreadContext<Impl>::dumpFuncProfile()
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
-
- VirtualPort *getVirtPort()
- { return thread->getVirtPort(); }
#else
TranslatingPort *getMemPort() { return thread->getMemPort(); }
Process *getProcessPtr() { return thread->getProcessPtr(); }
#endif
+ VirtualPort *getVirtPort()
+ { return thread->getVirtPort(); }
+
FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
Status status() const { return thread->status(); }
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
+#include "mem/vport.hh"
#include "params/BaseCPU.hh"
#if FULL_SYSTEM
#include "base/trace.hh"
#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
-#include "mem/vport.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#else
SimpleThread::~SimpleThread()
{
delete physPort;
-#if FULL_SYSTEM
delete virtPort;
-#endif
delete tc;
}
System *getSystemPtr() { return system; }
-#if FULL_SYSTEM
+ FunctionalPort *getPhysPort() { return physPort; }
+
/** Return a virtual port. This port cannot be cached locally in an object.
* After a CPU switch it may point to the wrong memory object which could
* mean stale data.
*/
VirtualPort *getVirtPort() { return virtPort; }
-#endif
-
- FunctionalPort *getPhysPort() { return physPort; }
Status status() const { return _status; }
#if FULL_SYSTEM
virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
- virtual VirtualPort *getVirtPort() = 0;
-
virtual void connectMemPorts(ThreadContext *tc) = 0;
#else
virtual TranslatingPort *getMemPort() = 0;
virtual Process *getProcessPtr() = 0;
#endif
+ virtual VirtualPort *getVirtPort() = 0;
+
virtual FunctionalPort *getPhysPort() = 0;
virtual Status status() const = 0;
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
- VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
-
void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
#else
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
+ VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
+
FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
Status status() const { return actualTC->status(); }
#include "cpu/thread_state.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
+#include "mem/vport.hh"
#include "sim/serialize.hh"
#if FULL_SYSTEM
#include "arch/kernel_stats.hh"
#include "cpu/quiesce_event.hh"
-#include "mem/vport.hh"
#endif
#if FULL_SYSTEM
baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
#if FULL_SYSTEM
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
- kernelStats(NULL), virtPort(NULL),
+ kernelStats(NULL),
#else
port(NULL), process(_process),
#endif
- physPort(NULL), funcExeInst(0), storeCondFailures(0)
+ virtPort(NULL), physPort(NULL), funcExeInst(0), storeCondFailures(0)
{
}
connectToMemFunc(physPort);
}
-#if FULL_SYSTEM
-void
-ThreadState::connectMemPorts(ThreadContext *tc)
-{
- connectPhysPort();
- connectVirtPort(tc);
-}
-
void
ThreadState::connectVirtPort(ThreadContext *tc)
{
connectToMemFunc(virtPort);
}
+#if FULL_SYSTEM
+void
+ThreadState::connectMemPorts(ThreadContext *tc)
+{
+ connectPhysPort();
+ connectVirtPort(tc);
+}
+
void
ThreadState::profileClear()
{
void connectPhysPort();
+ void connectVirtPort(ThreadContext *tc);
+
#if FULL_SYSTEM
void connectMemPorts(ThreadContext *tc);
- void connectVirtPort(ThreadContext *tc);
-
void dumpFuncProfile();
EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
void profileSample();
TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
-
- VirtualPort *getVirtPort() { return virtPort; }
#else
Process *getProcessPtr() { return process; }
void setMemPort(TranslatingPort *_port) { port = _port; }
#endif
+ VirtualPort *getVirtPort() { return virtPort; }
+
FunctionalPort *getPhysPort() { return physPort; }
void setPhysPort(FunctionalPort *port) { physPort = port; }
TheISA::Kernel::Statistics *kernelStats;
protected:
- /** A functional port, outgoing only, for functional accesse to virtual
- * addresses. */
- VirtualPort *virtPort;
#else
TranslatingPort *port;
Process *process;
#endif
+ /** A functional port, outgoing only, for functional accesse to virtual
+ * addresses. */
+ VirtualPort *virtPort;
+
/** A functional port outgoing only for functional accesses to physical
* addresses.*/
FunctionalPort *physPort;
Source('bridge.cc')
Source('bus.cc')
Source('mem_object.cc')
+Source('mport.cc')
Source('packet.cc')
Source('port.cc')
Source('tport.cc')
-Source('mport.cc')
+Source('vport.cc')
if env['TARGET_ISA'] != 'no':
SimObject('PhysicalMemory.py')
Source('dram.cc')
Source('physical.cc')
-if env['FULL_SYSTEM']:
- Source('vport.cc')
-elif env['TARGET_ISA'] != 'no':
+if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
Source('page_table.cc')
Source('translating_port.cc')