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diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 331ad9b303ae52111bd65b164c79a236132c974f..66fc14a4e93c501a910c7e1649efe1e136c7ca8e 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -59,7 +59,7 @@ and DSP.
 * 6 - Bitmanip LUT2/3 operations. high cost high reward [[sv/bitmanip]]
 * 1 - fclass (Scalar variant of xvtstdcsp) [[sv/fclass]]
 * 5 - Audio-Video [[sv/av_opcodes]]
-* 2 - Shift-and-Add (mitigates LD-ST-Shift; Cryptography e.g. twofish)
+* 2 - Shift-and-Add (mitigates LD-ST-Shift; Cryptography e.g. twofish) [[ls004]]
 * 2 - BMI group [[sv/vector_ops]]
 * 2 - GPU swizzle [[sv/mv.swizzle]]
 * 9 - FP DCT/FFT Butterfly (2/3-in 2-out)
@@ -139,7 +139,7 @@ was giiven instead to transferring several CR Field bits into GPRs, whereupon
 the full set of tandard Scalar GPR Logical Operations may be used. This strategy
 has the side-effect of keeping the CRweird group down to only five instructions.
 
-# Big-integer Math
+## Big-integer Math
 
 [[sv/biginteger]]  has always been a high priority area for commercial applications, privacy,
 Banking, as well as HPC Numerical Accuracy: libgmp as well as cryptographic uses
@@ -238,7 +238,7 @@ instuction.
 
 Thus they qualify as both high priority and also EXT0xx candidates.
 
-#  FPR/GPR LD/ST-PostIncrement-Update 
+## FPR/GPR LD/ST-PostIncrement-Update 
 
 These instruction, outlined in [[ls011]], save hugely in hot-loops.  Early ISAs
 such as PDP-8, PDP-11, which inspired the iconic Motorola 68000, 88100, Mitch
@@ -256,6 +256,21 @@ that outside the loop a "pre-subtraction" may be performed.
 Whilst this is a "solution" it is less than ideal, and the opportunity exists now
 with the EXT2xx Primary Opcodes to correct this and bring Power ISA up a level.
 
+## Shift-and-add
+
+Shift-and-Add are proposed in [[ls004]].  They mitigate the need to
+add LD-ST-Shift instructions which are a high-priority aspect of both
+x86 and ARM.  LD-ST-Shift is normally just the one instruction: Shift-and-add
+brings that down to two, where Power ISA presently requires three.
+Cryptography e.g. twofish also makes use of Integer double-and-add, so the value
+of these instructions is not limited to Effective Address computation.
+They will also have value in Audio DSP.
+
+Being a 10-bit XO it would be somewhat punitive to place these in EXT2xx when their
+whole purpose and value is to reduce binary size in Address offset computation,
+thus they are best placed in EXT0xx.
+
+
 
 
 [[!inline pages="openpower/sv/rfc/ls012/areas.mdwn" raw=yes ]]