/* Each texture is an array of slices. Each slice is an array
* of mipmap levels. */
return box->z * rtex->surface.u.gfx9.surf_slice_size +
- ((rtex->surface.u.gfx9.surf_ymip_offset[level] +
- box->y / rtex->surface.blk_h) *
+ rtex->surface.u.gfx9.offset[level] +
+ (box->y / rtex->surface.blk_h *
rtex->surface.u.gfx9.surf_pitch +
box->x / rtex->surface.blk_w) * rtex->surface.bpe;
} else {
* Use the staging texture for uploads if the underlying BO
* is busy.
*/
- /* TODO: Linear CPU mipmap addressing is broken on GFX9: */
- if (!rtex->surface.is_linear ||
- (rctx->chip_class == GFX9 && level))
+ if (!rtex->surface.is_linear)
use_staging_texture = true;
else if (usage & PIPE_TRANSFER_READ)
use_staging_texture =
uint64_t surf_slice_size;
uint16_t surf_pitch; /* in blocks */
uint16_t surf_height;
- /* Y mipmap level offset in blocks. Only valid for LINEAR. */
- uint16_t surf_ymip_offset[RADEON_SURF_MAX_LEVELS];
+ /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
+ uint32_t offset[RADEON_SURF_MAX_LEVELS];
uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */
if (in->swizzleMode == ADDR_SW_LINEAR) {
for (unsigned i = 0; i < in->numMipLevels; i++)
- surf->u.gfx9.surf_ymip_offset[i] = mip_info[i].mipOffsetYPixel;
+ surf->u.gfx9.offset[i] = mip_info[i].offset;
}
if (in->flags.depth) {