add RS3 replacement

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index f0759bc6d152901203aa79d60b34731dc9f6f5cd..283543ac42bff1f3e5941e8da78cbe6fd3c0a31a 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -23,6 +23,11 @@ reg_t sv_proc_t::get_rs2()
     return insn->p->get_state()->XPR[insn->rs2()];
 }
 
+reg_t sv_proc_t::get_rs3()
+{
+    return insn->p->get_state()->XPR[insn->rs3()];
+}
+
 freg_t sv_proc_t::get_frs1()
 {
     return READ_FREG(insn->rs1());

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index cb4848ae769249db206deda5f63f8f887a41864e..64338e0112e8cd511c87163c776bde1a88b54cb2 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -7,25 +7,16 @@
 
 #undef RS1
 #undef RS2
+#undef RS3
 #undef FRS1
 
 class processor_t;
 class insn_t;
 
-/*
-class FRS1 {
-    public:
-        sv_insn_t *_insn;
-        FRS1() : _insn(NULL) {}
-        //sv_insn_t & operator = (sv_insn_t &i)
-        //{ _insn = &i; return i; }
-        operator freg_t () const &;
-};
-*/
-
 #define FRS1 get_frs1()
 #define RS1 get_rs1()
 #define RS2 get_rs2()
+#define RS3 get_rs3()
 
 /*
 class RS2 {
@@ -54,6 +45,7 @@ public:
 
     reg_t get_rs1();
     reg_t get_rs2();
+    reg_t get_rs3();
 
     freg_t get_frs1();