arm: Fixes for asm-flags vs thumb1 and ilp32

Thumb1 cannot support asm-flags currently, because we don't expose the
flags register to the compiler.  Disable the support for that case.

Adjust the asm-flag-6 test for aarch64 ilp32 correctness.

gcc/
	* config/arm/arm-c.c (arm_cpu_builtins): Use def_or_undef_macro
	to define __GCC_ASM_FLAG_OUTPUTS__.
	* config/arm/arm.c (thumb1_md_asm_adjust): New function.
	(arm_option_params_internal): Swap out targetm.md_asm_adjust
	depending on TARGET_THUMB1.
	* doc/extend.texi (FlagOutputOperands): Document thumb1 restriction.

gcc/testsuite/
	* testsuite/gcc.target/arm/asm-flag-3.c: Skip for thumb1.
	* testsuite/gcc.target/arm/asm-flag-5.c: Likewise.
	* testsuite/gcc.target/arm/asm-flag-6.c: Likewise.
	* testsuite/gcc.target/arm/asm-flag-4.c: New test.

	* testsuite/gcc.target/aarch64/asm-flag-6.c: Use %w for
	asm inputs to cmp instruction for ILP32.

From-SVN: r278443

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index df949f184753742421169b483f8fb55bb6ffe9fb..1449ea4296216cd237751ca9e4fe526e0e9bbb18 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-11-19  Richard Henderson  <richard.henderson@linaro.org>
+
+       * config/arm/arm-c.c (arm_cpu_builtins): Use def_or_undef_macro
+       to define __GCC_ASM_FLAG_OUTPUTS__.
+       * config/arm/arm.c (thumb1_md_asm_adjust): New function.
+       (arm_option_params_internal): Swap out targetm.md_asm_adjust
+       depending on TARGET_THUMB1.
+       * doc/extend.texi (FlagOutputOperands): Document thumb1 restriction.
+
 2019-11-19  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/92549

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index c4485ce7af15f1fa135a3658677642ed18663968..546b35a5cbde2d877ed2e2d4a40c3dc1fcbdfb3d 100644 (file)
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -122,7 +122,8 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   if (arm_arch_notm)
     builtin_define ("__ARM_ARCH_ISA_ARM");
   builtin_define ("__APCS_32__");
-  builtin_define ("__GCC_ASM_FLAG_OUTPUTS__");
+
+  def_or_undef_macro (pfile, "__GCC_ASM_FLAG_OUTPUTS__", !TARGET_THUMB1);
 
   def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB);
   def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2);

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 1fd30c238cdb4c0c7db9966a78e41e8bb9d34140..a6b401b7f2e3738ff68316bd83d6e5a2bcf0e7d7 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -325,6 +325,9 @@ static unsigned int arm_hard_regno_nregs (unsigned int, machine_mode);
 static bool arm_hard_regno_mode_ok (unsigned int, machine_mode);
 static bool arm_modes_tieable_p (machine_mode, machine_mode);
 static HOST_WIDE_INT arm_constant_alignment (const_tree, HOST_WIDE_INT);
+static rtx_insn * thumb1_md_asm_adjust (vec<rtx> &, vec<rtx> &,
+                                       vec<const char *> &, vec<rtx> &,
+                                       HARD_REG_SET &);
 \f
 /* Table of machine attributes.  */
 static const struct attribute_spec arm_attribute_table[] =
@@ -2941,6 +2944,11 @@ arm_option_params_internal (void)
   /* For THUMB2, we limit the conditional sequence to one IT block.  */
   if (TARGET_THUMB2)
     max_insns_skipped = MIN (max_insns_skipped, MAX_INSN_PER_IT_BLOCK);
+
+  if (TARGET_THUMB1)
+    targetm.md_asm_adjust = thumb1_md_asm_adjust;
+  else
+    targetm.md_asm_adjust = arm_md_asm_adjust;
 }
 
 /* True if -mflip-thumb should next add an attribute for the default
@@ -32528,6 +32536,23 @@ arm_run_selftests (void)
 #define TARGET_RUN_TARGET_SELFTESTS selftest::arm_run_selftests
 #endif /* CHECKING_P */
 
+/* Worker function for TARGET_MD_ASM_ADJUST, while in thumb1 mode.
+   Unlike the arm version, we do NOT implement asm flag outputs.  */
+
+rtx_insn *
+thumb1_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/,
+                     vec<const char *> &constraints,
+                     vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/)
+{
+  for (unsigned i = 0, n = outputs.length (); i < n; ++i)
+    if (strncmp (constraints[i], "=@cc", 4) == 0)
+      {
+       sorry ("asm flags not supported in thumb1 mode");
+       break;
+      }
+  return NULL;
+}
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-arm.h"

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1c8ae0d5cd316f2af8b3f6458f0703c840efb545..62a98e939c8fb5edf47180b675766eae1a0494a5 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9810,6 +9810,8 @@ signed greater than
 signed less than equal
 @end table
 
+The flag output constraints are not supported in thumb1 mode.
+
 @item x86 family
 The flag output constraints for the x86 family are of the form
 @samp{=@@cc@var{cond}} where @var{cond} is one of the standard

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 51e8e1fc1c56329670a2d5b0f8a95d37851e0bba..1eb5f3cb8fa2895253bcdfb1b995dd0dad219b23 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2019-11-19  Richard Henderson  <richard.henderson@linaro.org>
+
+       * testsuite/gcc.target/arm/asm-flag-3.c: Skip for thumb1.
+       * testsuite/gcc.target/arm/asm-flag-5.c: Likewise.
+       * testsuite/gcc.target/arm/asm-flag-6.c: Likewise.
+       * testsuite/gcc.target/arm/asm-flag-4.c: New test.
+
+       * testsuite/gcc.target/aarch64/asm-flag-6.c: Use %w for
+       asm inputs to cmp instruction for ILP32.
+
 2019-11-19  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/92549

diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
index 963b5a48c70d50234c900f31615cf0f4bbeaa9d9..54d7fbf317d1f4e20e9035430614512783138022 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
@@ -1,6 +1,12 @@
 /* Executable testcase for 'output flags.'  */
 /* { dg-do run } */
 
+#ifdef __LP64__
+#define W ""
+#else
+#define W "w"
+#endif
+
 int test_bits (long nzcv)
 {
   long n, z, c, v;
@@ -16,7 +22,7 @@ int test_cmps (long x, long y)
 {
   long gt, lt, ge, le;
 
-  __asm__ ("cmp %[x], %[y]"
+  __asm__ ("cmp %"W"[x], %"W"[y]"
           : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
           : [x] "r"(x), [y] "r"(y));
 
@@ -30,7 +36,7 @@ int test_cmpu (unsigned long x, unsigned long y)
 {
   long gt, lt, ge, le;
 
-  __asm__ ("cmp %[x], %[y]"
+  __asm__ ("cmp %"W"[x], %"W"[y]"
           : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le)
           : [x] "r"(x), [y] "r"(y));
 

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
index 9707ebfcebb61ca1ee80cfe4765c869a407b711c..97104d3ac73ad95f90ca4ec71f3d968c495283f8 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/asm-flag-1.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
@@ -1,6 +1,7 @@
 /* Test the valid @cc<cc> asm flag outputs.  */
 /* { dg-do compile } */
 /* { dg-options "-O" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 #ifndef __GCC_ASM_FLAG_OUTPUTS__
 #error "missing preprocessor define"

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
index e84e3431277d3d0f2ca22471dd3c58a7c12c601b..e2d616051cc5262b21b219b9c3016ab6a646cf17 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/asm-flag-3.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
@@ -1,6 +1,7 @@
 /* Test some of the valid @cc<cc> asm flag outputs.  */
 /* { dg-do compile } */
 /* { dg-options "-O" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 #define DO(C) \
 void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-4.c b/gcc/testsuite/gcc.target/arm/asm-flag-4.c
new file mode 100644 (file)
index 0000000..3791cad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-4.c
@@ -0,0 +1,13 @@
+/* Test that we do not ice in thumb1 mode */
+/* { dg-do compile } */
+/* { dg-options "-march=armv4t" } */
+
+void __attribute__((target("arm"))) f(char *out)
+{
+  asm("" : "=@ccne"(out[0]));
+}
+
+void __attribute__((target("thumb"))) g(char *out)
+{
+  asm("" : "=@ccne"(out[0]));  /* { dg-error asm flags not supported } */
+}

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
index 4d4394e1478273c5af77283916f5367ea4134fe7..9a8ff586c297371b357310c5867dfdc16ef87000 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/asm-flag-5.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
@@ -1,6 +1,7 @@
 /* Test error conditions of asm flag outputs.  */
 /* { dg-do compile } */
 /* { dg-options "" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }
 void f_c(void) { char x; asm("" : "=@cccc"(x)); }

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
index 09174e04ae6cc41ee265aec64c0445e8611d29c0..d862db4e106301952a5707df0965703d9e76bce6 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/asm-flag-6.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
@@ -1,5 +1,6 @@
 /* Executable testcase for 'output flags.'  */
 /* { dg-do run } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 int test_bits (long nzcv)
 {