i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.

Skylake has separate controls for enabling the Z Clip Test for the near
and far planes.  For now, maintain the legacy behavior by setting both.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 950f97a1368f21484dcd44c4d8273bdfb583f491..3725452bc9804c7280275c6dbb41a52d2cf54892 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1914,6 +1914,7 @@ enum brw_message_target {
 
 #define _3DSTATE_RASTER                         0x7850 /* GEN8+ */
 /* DW1 */
+# define GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE    (1 << 26)
 # define GEN8_RASTER_FRONT_WINDING_CCW                  (1 << 21)
 # define GEN8_RASTER_CULL_BOTH                          (0 << 16)
 # define GEN8_RASTER_CULL_NONE                          (1 << 16)
@@ -1924,6 +1925,7 @@ enum brw_message_target {
 # define GEN8_RASTER_LINE_AA_ENABLE                     (1 << 2)
 # define GEN8_RASTER_SCISSOR_ENABLE                     (1 << 1)
 # define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE        (1 << 0)
+# define GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE   (1 << 0)
 
 /* Gen8 BLEND_STATE */
 /* DW0 */

diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 0a15d9c2984ff3565b4d21ae5e654d22ffcc4d33..1d7b93261ac890f2caa2515495af856d6499fe53 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -291,8 +291,14 @@ upload_raster(struct brw_context *brw)
       dw1 |= GEN8_RASTER_SCISSOR_ENABLE;
 
    /* _NEW_TRANSFORM */
-   if (!ctx->Transform.DepthClamp)
-      dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE;
+   if (!ctx->Transform.DepthClamp) {
+      if (brw->gen >= 9) {
+         dw1 |= GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE |
+                GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE;
+      } else {
+         dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE;
+      }
+   }
 
    BEGIN_BATCH(5);
    OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));