sort out sv.cmp zz (and correct unit tests)

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 1e3a2e739c56c5702f32b994481244106a9014e3..1e909669207f0617f40fd850c81e7950b932a8c2 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -2344,14 +2344,12 @@ class CROpFF5RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CRO
 
 # FIXME: almost everything in this class contradicts the specs (it doesn't)
 # The modes however are swapped: 5-bit is 3-bit, 3-bit is 5-bit
-class CROpFF3RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, CROpBaseRM):
+class CROpFF3RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, ZZBaseRM, CROpBaseRM):
     """cr_op: ffirst 3-bit mode"""
-    RC1 = 0 # temporary hack
     VLi: BaseRM[19]
     inv: BaseRM[21]
     CR: BaseRM[22, 23]
-    dz: BaseRM[22]
-    sz: BaseRM[23]
+    zz: BaseRM[6]
 
     def specifiers(self, record):
         yield from super().specifiers(record=record, mode="ff")

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 273abaff07dc32844a7f163528f0623b327d2abe..2fa016429e4f6204fbfdc7d35e63b2ec1a4c9f75 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -72,7 +72,7 @@ class SVSTATETestCase(unittest.TestCase):
         expected = [
                     'sv.crand *16,*2,*33',
                     'sv.crand 12,2,33',
-                    'sv.crand/ff=eq/m=r10 12,2,33',
+                    'sv.crand/ff=RC1/m=r10 12,2,33',
                     'sv.crand/m=r10 12,2,33',
                     'sv.crand/m=r10/sz 12,2,33',
                     'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
@@ -318,9 +318,9 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.cmp/ff=eq *4,1,*0,1",
                     "sv.cmp/ff=eq/vli *4,1,*0,1",
                     "sv.cmp/ff=ne *4,1,*0,1",
-                    "sv.cmp/ff=eq/m=r3/sz *4,1,*0,1",
-                    "sv.cmp/dz/ff=lt/m=r3 *4,1,*0,1",
-                    "sv.cmp/dz/ff=gt/m=r3/sz *4,1,*0,1",
+                    "sv.cmp/ff=eq/m=r3/zz *4,1,*0,1",
+                    "sv.cmp/ff=lt/m=r3/zz *4,1,*0,1",
+                    "sv.cmp/ff=gt/m=r3/zz *4,1,*0,1",
                         ]
         self._do_tst(expected)