/* VPU only on TCL */
if (has_tcl) {
+ int i;
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
r300->hw.vpi.cmd[R300_VPI_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_PROGRAM, 0);
+
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[R300_VPP_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_PARAMETERS, 0);
+
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[R300_VPS_CMD_0] =
cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1);
+
+ for (i = 0; i < 6; i++) {
+ ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
+ r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
+ cmdvpu(R300_PVS_UPLOAD_CLIP_PLANE0+i, 1);
+ }
}
/* Textures */
#define R300_VPP_PARAM_0 1
#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
+#define R300_VPUCP_CMD_0 0
+#define R300_VPUCP_X 1
+#define R300_VPUCP_Y 2
+#define R300_VPUCP_Z 3
+#define R300_VPUCP_W 4
+#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
+
#define R300_VPS_CMD_0 0
#define R300_VPS_ZERO_0 1
#define R300_VPS_ZERO_1 2
struct r300_state_atom vpi; /* vp instructions */
struct r300_state_atom vpp; /* vp parameters */
struct r300_state_atom vps; /* vertex point size (?) */
+ struct r300_state_atom vpucp[6]; /* vp user clip plane - 6 */
/* 8 texture units */
/* the state is grouped by function and not by
texture unit. This makes single unit updates
# define R300_PVS_UPLOAD_CLIP_PLANE5 0x00000405
# define R300_PVS_UPLOAD_POINTSIZE 0x00000406
+# define R500_PVS_UPLOAD_CLIP_PLANE0 0x00000600
+# define R500_PVS_UPLOAD_CLIP_PLANE1 0x00000601
+# define R500_PVS_UPLOAD_CLIP_PLANE2 0x00000602
+# define R500_PVS_UPLOAD_CLIP_PLANE3 0x00000603
+# define R500_PVS_UPLOAD_CLIP_PLANE4 0x00000604
+# define R500_PVS_UPLOAD_CLIP_PLANE5 0x00000605
+
/*
* These are obsolete defines form r300_context.h, but they might give some
* clues when investigating the addresses further...
#define R300_VAP_UNKNOWN_221C 0x221C
# define R300_221C_NORMAL 0x00000000
# define R300_221C_CLEAR 0x0001C000
+#define R300_VAP_UCP_ENABLE_0 (1 << 0)
/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
* plane is per-pixel and the second plane is per-vertex.
extern int future_hw_tcl_on;
extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx);
+static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq );
static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4])
{
static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
-
+ GLuint p;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(cap),
r300SetBlendState(ctx);
break;
+
+ case GL_CLIP_PLANE0:
+ case GL_CLIP_PLANE1:
+ case GL_CLIP_PLANE2:
+ case GL_CLIP_PLANE3:
+ case GL_CLIP_PLANE4:
+ case GL_CLIP_PLANE5:
+ /* no VAP UCP on non-TCL chipsets */
+ if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ return;
+
+ p = cap-GL_CLIP_PLANE0;
+ R300_STATECHANGE( r300, unk221C );
+ if (state) {
+ r300->hw.unk221C.cmd[1] |= (R300_VAP_UCP_ENABLE_0<<p);
+ r300ClipPlane( ctx, cap, NULL );
+ }
+ else {
+ r300->hw.unk221C.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0<<p);
+ }
+ break;
case GL_DEPTH_TEST:
r300SetDepthState(ctx);
break;
r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
}
break;
+
+
default:
radeonEnable(ctx, cap, state);
return;
(void)mode;
}
+static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
+{
+ r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
+ GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
+
+ R300_STATECHANGE( rmesa, vpucp[p] );
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
+}
+
+
+void r300UpdateClipPlanes( GLcontext *ctx )
+{
+ r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ GLuint p;
+
+ for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
+ if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
+ GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
+
+ R300_STATECHANGE( rmesa, vpucp[p] );
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
+ }
+ }
+}
+
/**
* Initialize driver's state callback functions
*/
functions->PolygonMode = r300PolygonMode;
functions->RenderMode = r300RenderMode;
+
+ functions->ClipPlane = r300ClipPlane;
}