h8300.md (mulqihi3): Tighten predicates to register_operand.

	* config/h8300/h8300.md (mulqihi3): Tighten predicates to
	register_operand.
	(mulhisi3): Likewise.
	(umulqisi3): Likewise.
	(umulhisi3): Likewise.

From-SVN: r49994

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6e6db2802c63115b7bb39dce104eb875008254b0..bc546ad344ede4fa57e080f3d317f340b79f4bed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2002-02-23  Kazu Hirata  <kazu@hxi.com>
+
+       * config/h8300/h8300.md (mulqihi3): Tighten predicates to
+       register_operand.
+       (mulhisi3): Likewise.
+       (umulqisi3): Likewise.
+       (umulhisi3): Likewise.
+
 2002-02-23  Neil Booth  <neil@daikokuya.demon.co.uk>
 
        * cppinit.c (output_deps): Correct test for stdout output.

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index b9dc64032227e58d3f40b753be70f336aba6bc3c..d99103efa60cc7bb9763bd4ae08ca60ebca762ca 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -841,7 +841,7 @@
 
 (define_insn "mulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-       (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
+       (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
                 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
   "TARGET_H8300H || TARGET_H8300S"
   "mulxs.b     %X2,%T0"
@@ -850,7 +850,7 @@
 
 (define_insn "mulhisi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
+       (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
                 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
   "TARGET_H8300H || TARGET_H8300S"
   "mulxs.w     %T2,%S0"
@@ -859,7 +859,7 @@
 
 (define_insn "umulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-       (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
+       (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
                 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
   ""
   "mulxu       %X2,%T0"
@@ -868,7 +868,7 @@
 
 (define_insn "umulhisi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
+       (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
                 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
   "TARGET_H8300H || TARGET_H8300S"
   "mulxu.w     %T2,%S0"