ARM: Make some of the trace code more compact

diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 3dde0aa35dbfb40c811ddd7bb31e0b7ea7bc9e12..552803b6af456c4f53a8b4bc9d3f921e9a27b3d1 100644 (file)
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -60,18 +60,10 @@ MemoryReg::printOffset(std::ostream &os) const
             ccprintf(os, " LSL #%d", shiftAmt);
             break;
           case LSR:
-            if (shiftAmt == 0) {
-                ccprintf(os, " LSR #%d", 32);
-            } else {
-                ccprintf(os, " LSR #%d", shiftAmt);
-            }
+            ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
             break;
           case ASR:
-            if (shiftAmt == 0) {
-                ccprintf(os, " ASR #%d", 32);
-            } else {
-                ccprintf(os, " ASR #%d", shiftAmt);
-            }
+            ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
             break;
           case ROR:
             if (shiftAmt == 0) {