add read_verilog when using external core

diff --git a/Makefile b/Makefile
index 395cc5e51843ab2784cd82b9015b377ed44df932..aff1b193d1f053f71612eca4f2eea53b7620bf5e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -249,6 +249,9 @@ ifeq ($(EXTERNAL_CORE),false)
                nonrandom.vhdl
 
        synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+       
+microwatt.v: $(synth_files) $(RAM_INIT_FILE)
+       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 else
 #incomplete: does not build yet
     util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
@@ -256,15 +259,14 @@ else
     fpga_files = $(_fpga_files) $(_soc_files)
     synth_files = $(util_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
     soc_extra_v = external_core_top.v
+microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(soc_extra_v)
+       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); write_verilog $@"
 endif
 #--
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE) $(soc_extra_v)
        $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
 
-microwatt.v: $(synth_files) $(RAM_INIT_FILE)
-       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
-
 microwatt-verilator-broken: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
        $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
        @cp -f obj_dir/microwatt-verilator microwatt-verilator