(one_cmpldi2): New pattern.

({a,l}shrdi{3,_const}): Allow 63 as shift count.

From-SVN: r9854

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index d2667ea131b229dfab9253712885a90eae7b6984..fab11593df0865f25625915766cf93b51f744ab3 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -4009,6 +4009,24 @@
 \f
 ;; one complement instructions
 
+;; "one_cmpldi2" is only here to help combine().
+(define_insn "one_cmpldi2"
+  [(set (match_operand:DI 0 "general_operand" "=dm")
+       (not:DI (match_operand:DI 1 "general_operand" "0")))]
+  ""
+  "*
+{
+  CC_STATUS_INIT;
+  if (GET_CODE (operands[0]) == REG)
+    operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
+        || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    operands[1] = operands[0];
+  else
+    operands[1] = adj_offsettable_operand (operands[0], 4);
+  return \"not%.l %1\;not%.l %0\";
+}")
+
 (define_insn "one_cmplsi2"
   [(set (match_operand:SI 0 "general_operand" "=dm")
        (not:SI (match_operand:SI 1 "general_operand" "0")))]
@@ -4293,12 +4311,14 @@
   [(set (match_operand:DI 0 "general_operand" "=d")
        (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
                     (match_operand 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) == 1
-    || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
-  || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
+  "(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
+    || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
+    || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
   "*
 {
   operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  if (INTVAL (operands[2]) == 63)
+    return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
   CC_STATUS_INIT;
   if (INTVAL (operands[2]) == 1)
     return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
@@ -4320,9 +4340,10 @@
   "
 {
   if (GET_CODE (operands[2]) != CONST_INT
-  || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
-     && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
-     && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
+  || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
+     && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
+     && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
+     && INTVAL (operands[2]) != 63))
     FAIL;
 } ")
 
@@ -4434,13 +4455,15 @@
   [(set (match_operand:DI 0 "general_operand" "=d")
        (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
                     (match_operand 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) == 1 
-    || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
-    || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
+  "(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
+    || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
+    || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
   "*
 {
-  CC_STATUS_INIT;
   operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  if (INTVAL (operands[2]) == 63)
+    return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
+  CC_STATUS_INIT;
   if (INTVAL (operands[2]) == 1)
     return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
   else if (INTVAL (operands[2]) == 8)
@@ -4461,9 +4484,10 @@
   "
 {
   if (GET_CODE (operands[2]) != CONST_INT
-  || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
-     && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
-      && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
+  || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
+     && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
+     && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
+     && INTVAL (operands[2]) != 63))
     FAIL;
 } ")