bits[i-1] == RTLIL::S1 ? '1' :
bits[i-1] == RTLIL::Sx ? 'x' :
bits[i-1] == RTLIL::Sz ? 'z' : '?');
- fprintf(f, "'(%zd)", bits.size());
+ fprintf(f, "'(%d)", GetSize(bits));
}
if (is_input)
fprintf(f, " input");
else if (bits.size() == 32)
fprintf(f, "%d", RTLIL::Const(bits).as_int());
else
- fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
+ fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
break;
case AST_REALVALUE:
if (merged_set.size() > 0 && !already_optimized)
FsmData::optimize_fsm(fsm_cell, module);
- log(" merged %zd cells into FSM.\n", merged_set.size());
+ log(" merged %d cells into FSM.\n", GetSize(merged_set));
}
};
prefix, RTLIL::unescape_id(module->name).c_str());
fprintf(f, "set_fsm_encoding {");
- for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
- fprintf(f, " s%zd=2#", i);
- for (int j = int(fsm_data.state_table[i].bits.size())-1; j >= 0; j--)
+ for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
+ fprintf(f, " s%d=2#", i);
+ for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
}
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
delete mod;
}
- log("Removed %zd unused modules.\n", del_modules.size());
+ log("Removed %d unused modules.\n", GetSize(del_modules));
}
bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
for (auto &mi : mux2info)
{
std::vector<int> live_ports;
- for (size_t port_idx = 0; port_idx < mi.ports.size(); port_idx++) {
+ for (int port_idx = 0; port_idx < GetSize(mi.ports); port_idx++) {
portinfo_t &pi = mi.ports[port_idx];
if (pi.enabled) {
live_ports.push_back(port_idx);
} else {
- log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(),
+ log(" dead port %d/%d on %s %s.\n", port_idx+1, GetSize(mi.ports),
mi.cell->type.c_str(), mi.cell->name.c_str());
removed_count++;
}