r600g: compute tiling info in the pipe, not in the winsys

The winsys doesn't need it.

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index f24146edcf10e7cad763736ac14281c5abf55107..600fae94b790b18c368e6a36d54411366c6ad9d8 100644 (file)
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -84,7 +84,6 @@ struct r600_tiling_info {
 
 enum radeon_family r600_get_family(struct radeon *rw);
 enum chip_class r600_get_family_class(struct radeon *radeon);
-struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
 unsigned r600_get_minor_version(struct radeon *radeon);
 unsigned r600_get_num_backends(struct radeon *radeon);

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index a3fc61822e7930a41c5da5ac4332efc94ff15ce1..7c8480772d2578770182e4a67e98360ded59221b 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -589,18 +589,140 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen,
        return TRUE;
 }
 
+static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
+{
+       switch ((tiling_config & 0xe) >> 1) {
+       case 0:
+               rscreen->tiling_info.num_channels = 1;
+               break;
+       case 1:
+               rscreen->tiling_info.num_channels = 2;
+               break;
+       case 2:
+               rscreen->tiling_info.num_channels = 4;
+               break;
+       case 3:
+               rscreen->tiling_info.num_channels = 8;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       switch ((tiling_config & 0x30) >> 4) {
+       case 0:
+               rscreen->tiling_info.num_banks = 4;
+               break;
+       case 1:
+               rscreen->tiling_info.num_banks = 8;
+               break;
+       default:
+               return -EINVAL;
+
+       }
+       switch ((tiling_config & 0xc0) >> 6) {
+       case 0:
+               rscreen->tiling_info.group_bytes = 256;
+               break;
+       case 1:
+               rscreen->tiling_info.group_bytes = 512;
+               break;
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
+{
+       switch (tiling_config & 0xf) {
+       case 0:
+               rscreen->tiling_info.num_channels = 1;
+               break;
+       case 1:
+               rscreen->tiling_info.num_channels = 2;
+               break;
+       case 2:
+               rscreen->tiling_info.num_channels = 4;
+               break;
+       case 3:
+               rscreen->tiling_info.num_channels = 8;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       switch ((tiling_config & 0xf0) >> 4) {
+       case 0:
+               rscreen->tiling_info.num_banks = 4;
+               break;
+       case 1:
+               rscreen->tiling_info.num_banks = 8;
+               break;
+       case 2:
+               rscreen->tiling_info.num_banks = 16;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       switch ((tiling_config & 0xf00) >> 8) {
+       case 0:
+               rscreen->tiling_info.group_bytes = 256;
+               break;
+       case 1:
+               rscreen->tiling_info.group_bytes = 512;
+               break;
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static int r600_init_tiling(struct r600_screen *rscreen)
+{
+       uint32_t tiling_config = rscreen->info.r600_tiling_config;
+
+       /* set default group bytes, overridden by tiling info ioctl */
+       if (r600_get_family_class(rscreen->radeon) <= R700) {
+               rscreen->tiling_info.group_bytes = 256;
+       } else {
+               rscreen->tiling_info.group_bytes = 512;
+       }
+
+       if (!tiling_config)
+               return 0;
+
+       if (r600_get_family_class(rscreen->radeon) <= R700) {
+               return r600_interpret_tiling(rscreen, tiling_config);
+       } else {
+               return evergreen_interpret_tiling(rscreen, tiling_config);
+       }
+}
+
 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 {
        struct r600_screen *rscreen;
        struct radeon *radeon = radeon_create(ws);
+       if (!radeon) {
+               return NULL;
+       }
 
        rscreen = CALLOC_STRUCT(r600_screen);
        if (rscreen == NULL) {
+               radeon_destroy(radeon);
                return NULL;
        }
 
        rscreen->ws = ws;
        rscreen->radeon = radeon;
+       ws->query_info(ws, &rscreen->info);
+
+       if (r600_init_tiling(rscreen)) {
+               radeon_destroy(radeon);
+               FREE(rscreen);
+               return NULL;
+       }
+
        rscreen->screen.winsys = (struct pipe_winsys*)ws;
        rscreen->screen.destroy = r600_destroy_screen;
        rscreen->screen.get_name = r600_get_name;
@@ -621,7 +743,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        rscreen->screen.fence_finish = r600_fence_finish;
        r600_init_screen_resource_functions(&rscreen->screen);
 
-       rscreen->tiling_info = r600_get_tiling_info(radeon);
        util_format_s3tc_init();
 
        util_slab_create(&rscreen->pool_buffers,

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index c495221436467c3f3d41ea3245ce422e8150da0a..7c7f0424a26684a4a68a3754bb00861a24c7a166 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -76,7 +76,8 @@ struct r600_screen {
        struct pipe_screen              screen;
        struct radeon_winsys            *ws;
        struct radeon                   *radeon;
-       struct r600_tiling_info         *tiling_info;
+       struct radeon_info              info;
+       struct r600_tiling_info         tiling_info;
        struct util_slab_mempool        pool_buffers;
        unsigned                        num_contexts;
 

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 425e269069fb1fd38a8d32f5e568af62187713cb..4c7c7e57414a56b0b381b7851a34b675542fb098 100644 (file)
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -93,19 +93,19 @@ static unsigned r600_get_block_alignment(struct pipe_screen *screen,
        switch(array_mode) {
        case V_038000_ARRAY_1D_TILED_THIN1:
                p_align = MAX2(8,
-                              ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
+                              ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
                break;
        case V_038000_ARRAY_2D_TILED_THIN1:
-               p_align = MAX2(rscreen->tiling_info->num_banks,
-                              (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
-                               rscreen->tiling_info->num_banks)) * 8;
+               p_align = MAX2(rscreen->tiling_info.num_banks,
+                              (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
+                               rscreen->tiling_info.num_banks)) * 8;
                break;
        case V_038000_ARRAY_LINEAR_ALIGNED:
-               p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
+               p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
                break;
        case V_038000_ARRAY_LINEAR_GENERAL:
        default:
-               p_align = rscreen->tiling_info->group_bytes / pixsize;
+               p_align = rscreen->tiling_info.group_bytes / pixsize;
                break;
        }
        return p_align;
@@ -119,7 +119,7 @@ static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 
        switch (array_mode) {
        case V_038000_ARRAY_2D_TILED_THIN1:
-               h_align = rscreen->tiling_info->num_channels * 8;
+               h_align = rscreen->tiling_info.num_channels * 8;
                break;
        case V_038000_ARRAY_1D_TILED_THIN1:
        case V_038000_ARRAY_LINEAR_ALIGNED:
@@ -145,14 +145,14 @@ static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 
        switch (array_mode) {
        case V_038000_ARRAY_2D_TILED_THIN1:
-               b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
+               b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
                               p_align * pixsize * h_align);
                break;
        case V_038000_ARRAY_1D_TILED_THIN1:
        case V_038000_ARRAY_LINEAR_ALIGNED:
        case V_038000_ARRAY_LINEAR_GENERAL:
        default:
-               b_align = rscreen->tiling_info->group_bytes;
+               b_align = rscreen->tiling_info.group_bytes;
                break;
        }
        return b_align;

diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 1917f87bcf6a93bce00bb18242226c5e897832f0..d9eeda9e9f8a3a56322f304c78f0520223f88eb1 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -41,11 +41,6 @@ enum chip_class r600_get_family_class(struct radeon *radeon)
        return radeon->chip_class;
 }
 
-struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon)
-{
-       return &radeon->tiling_info;
-}
-
 unsigned r600_get_clock_crystal_freq(struct radeon *radeon)
 {
        return radeon->info.r600_clock_crystal_freq;
@@ -71,110 +66,6 @@ unsigned r600_get_minor_version(struct radeon *radeon)
        return radeon->info.drm_minor;
 }
 
-static int r600_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
-{
-       switch ((tiling_config & 0xe) >> 1) {
-       case 0:
-               radeon->tiling_info.num_channels = 1;
-               break;
-       case 1:
-               radeon->tiling_info.num_channels = 2;
-               break;
-       case 2:
-               radeon->tiling_info.num_channels = 4;
-               break;
-       case 3:
-               radeon->tiling_info.num_channels = 8;
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       switch ((tiling_config & 0x30) >> 4) {
-       case 0:
-               radeon->tiling_info.num_banks = 4;
-               break;
-       case 1:
-               radeon->tiling_info.num_banks = 8;
-               break;
-       default:
-               return -EINVAL;
-
-       }
-       switch ((tiling_config & 0xc0) >> 6) {
-       case 0:
-               radeon->tiling_info.group_bytes = 256;
-               break;
-       case 1:
-               radeon->tiling_info.group_bytes = 512;
-               break;
-       default:
-               return -EINVAL;
-       }
-       return 0;
-}
-
-static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
-{
-       switch (tiling_config & 0xf) {
-       case 0:
-               radeon->tiling_info.num_channels = 1;
-               break;
-       case 1:
-               radeon->tiling_info.num_channels = 2;
-               break;
-       case 2:
-               radeon->tiling_info.num_channels = 4;
-               break;
-       case 3:
-               radeon->tiling_info.num_channels = 8;
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       switch ((tiling_config & 0xf0) >> 4) {
-       case 0:
-               radeon->tiling_info.num_banks = 4;
-               break;
-       case 1:
-               radeon->tiling_info.num_banks = 8;
-               break;
-       case 2:
-               radeon->tiling_info.num_banks = 16;
-               break;
-       default:
-               return -EINVAL;
-
-       }
-
-       switch ((tiling_config & 0xf00) >> 8) {
-       case 0:
-               radeon->tiling_info.group_bytes = 256;
-               break;
-       case 1:
-               radeon->tiling_info.group_bytes = 512;
-               break;
-       default:
-               return -EINVAL;
-       }
-       return 0;
-}
-
-static int radeon_drm_get_tiling(struct radeon *radeon)
-{
-       uint32_t tiling_config = radeon->info.r600_tiling_config;
-
-       if (!tiling_config)
-               return 0;
-
-       if (radeon->chip_class == R600 || radeon->chip_class == R700) {
-               return r600_interpret_tiling(radeon, tiling_config);
-       } else {
-               return eg_interpret_tiling(radeon, tiling_config);
-       }
-}
-
 static unsigned radeon_family_from_device(unsigned device)
 {
        switch (device) {
@@ -212,16 +103,12 @@ struct radeon *radeon_create(struct radeon_winsys *ws)
        case CHIP_RS780:
        case CHIP_RS880:
                radeon->chip_class = R600;
-               /* set default group bytes, overridden by tiling info ioctl */
-               radeon->tiling_info.group_bytes = 256;
                break;
        case CHIP_RV770:
        case CHIP_RV730:
        case CHIP_RV710:
        case CHIP_RV740:
                radeon->chip_class = R700;
-               /* set default group bytes, overridden by tiling info ioctl */
-               radeon->tiling_info.group_bytes = 256;
                break;
        case CHIP_CEDAR:
        case CHIP_REDWOOD:
@@ -235,13 +122,9 @@ struct radeon *radeon_create(struct radeon_winsys *ws)
        case CHIP_TURKS:
        case CHIP_CAICOS:
                radeon->chip_class = EVERGREEN;
-               /* set default group bytes, overridden by tiling info ioctl */
-               radeon->tiling_info.group_bytes = 512;
                break;
        case CHIP_CAYMAN:
                radeon->chip_class = CAYMAN;
-               /* set default group bytes, overridden by tiling info ioctl */
-               radeon->tiling_info.group_bytes = 512;
                break;
        default:
                fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
@@ -249,9 +132,6 @@ struct radeon *radeon_create(struct radeon_winsys *ws)
                break;
        }
 
-       if (radeon_drm_get_tiling(radeon))
-               return NULL;
-
        return radeon;
 }
 

diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 2b8c85a1431ba6da64439d99dc573d2bb4cf0a38..36a24377e79fe4e00b958e08821dc5e2d8c536ca 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -39,7 +39,6 @@ struct radeon {
        struct radeon_info              info;
        unsigned                        family;
        enum chip_class                 chip_class;
-       struct r600_tiling_info         tiling_info;
 };
 
 /* these flags are used in register flags and added into block flags */