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liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 9 Mar 2015 11:45:46 +0000 (12:45 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 9 Mar 2015 12:23:39 +0000 (13:23 +0100)
misoclib/com/liteeth/mac/frontend/sram.py patch | blob | history

diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py
index 7df9c58489b264b8b02e00b79deb8b1c466686d5..cb6a4d72ca5f737e0521b7301ccdc1251c540ca6 100644 (file)
--- a/misoclib/com/liteeth/mac/frontend/sram.py
+++ b/misoclib/com/liteeth/mac/frontend/sram.py
@@ -69,10 +69,10 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
                self.submodules += fsm
 
                fsm.act("IDLE",
-                       inc_cnt.eq(sink.stb),
                        If(sink.stb & sink.sop,
-                               ongoing.eq(1),
                                If(fifo.sink.ack,
+                                       ongoing.eq(1),
+                                       inc_cnt.eq(1),
                                        NextState("WRITE")
                                )
                        )