add comparison section

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index c9308e28f236d45d42a9853eb2e59305b355105d..6d7eba88f44fdd98e005aed703e27a091d4cd819 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1117,7 +1117,10 @@ RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft)
   be able to do so if "indirect" features of Simple-V are partially adopted).
 * plus-and-slight-minus: extended variants may address up to 256
   vectorised registers (requires 48/64-bit opcodes to do it).
-
+* minus-and-partial-plus: separate engine plus complexity increases
+  implementation time and die area, meaning that adoption is likely only
+  to be in high-performance specialist supercomputing (where it will
+  be absolutely superb).
 
 # Impementing V on top of Simple-V