subst.md (define_subst_attr "mask_avx512bw_condition"): New.

gcc/
	* config/i386/subst.md (define_subst_attr "mask_avx512bw_condition"):
	New.
	* config/i386/sse.md
	(define_mode_iterator VI248_AVX2): Delete.
	(define_mode_iterator VI2_AVX2_AVX512BW): New.
	(define_mode_iterator VI48_AVX2): Ditto.
	(define_insn <shift_insn><mode>3): Delete.
	(define_insn "<shift_insn><mode>3<mask_name>" with
	VI2_AVX2_AVX512BW): New.
	(define_insn "<shift_insn><mode>3<mask_name>" with
	VI48_AVX2): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r214310

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4023a3105cd612ffca8bd2f8612ddd2c9fe8dc2c..afae0ada54a8093f7ed0d99c1dd5a70b02b770f9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2014-08-22  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/subst.md (define_subst_attr "mask_avx512bw_condition"):
+       New.
+       * config/i386/sse.md
+       (define_mode_iterator VI248_AVX2): Delete.
+       (define_mode_iterator VI2_AVX2_AVX512BW): New.
+       (define_mode_iterator VI48_AVX2): Ditto.
+       (define_insn <shift_insn><mode>3): Delete.
+       (define_insn "<shift_insn><mode>3<mask_name>" with
+       VI2_AVX2_AVX512BW): New.
+       (define_insn "<shift_insn><mode>3<mask_name>" with
+       VI48_AVX2): Ditto.
+
 2014-08-22  Alexander Ivchenko  <alexander.ivchenko@intel.com>
            Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
            Anna Tikhonova  <anna.tikhonova@intel.com>

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 04ed6bd7df273b1e463a8d870ce2a45d0fc8be4d..5084892f2216f63e1e6698a701cf3bdbd69511a2 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -347,9 +347,11 @@
    (V16HI "TARGET_AVX2") V8HI
    (V8SI "TARGET_AVX2") V4SI])
 
-(define_mode_iterator VI248_AVX2
-  [(V16HI "TARGET_AVX2") V8HI
-   (V8SI "TARGET_AVX2") V4SI
+(define_mode_iterator VI2_AVX2_AVX512BW
+  [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
+
+(define_mode_iterator VI48_AVX2
+  [(V8SI "TARGET_AVX2") V4SI
    (V4DI "TARGET_AVX2") V2DI])
 
 (define_mode_iterator VI248_AVX2_8_AVX512F
@@ -8584,15 +8586,34 @@
        (const_string "0")))
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<shift_insn><mode>3"
-  [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
-       (any_lshift:VI248_AVX2
-         (match_operand:VI248_AVX2 1 "register_operand" "0,x")
-         (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
-  "TARGET_SSE2"
+(define_insn "<shift_insn><mode>3<mask_name>"
+  [(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v")
+       (any_lshift:VI2_AVX2_AVX512BW
+         (match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v")
+         (match_operand:SI 2 "nonmemory_operand" "xN,vN")))]
+  "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
+  "@
+   p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
+   vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand")
+       (const_string "1")
+       (const_string "0")))
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<shift_insn><mode>3<mask_name>"
+  [(set (match_operand:VI48_AVX2 0 "register_operand" "=x,v")
+       (any_lshift:VI48_AVX2
+         (match_operand:VI48_AVX2 1 "register_operand" "0,v")
+         (match_operand:SI 2 "nonmemory_operand" "xN,vN")))]
+  "TARGET_SSE2 && <mask_mode512bit_condition>"
   "@
    p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
-   vp<vshift><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+   vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseishft")
    (set (attr "length_immediate")

diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md
index edb0965ab3d3fa2c334753928c992403966681a3..b05cb17053de2657cb4dffba38df99926bb64689 100644 (file)
--- a/gcc/config/i386/subst.md
+++ b/gcc/config/i386/subst.md
@@ -56,6 +56,7 @@
 (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
 (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
 (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
+(define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
 (define_subst_attr "store_mask_constraint" "mask" "vm" "v")
 (define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
 (define_subst_attr "mask_prefix" "mask" "vex" "evex")